?? rijndael_en_top.vhd
字號:
----------------------------------------------------
--
-- Library Name : rijndael_min_new
-- Unit Name : DK_GEN_CTRL
-- Unit Type : State Machine
--
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library ieee;use ieee.STD_LOGIC_1164.all;use ieee.NUMERIC_STD.all;use ieee.STD_LOGIC_UNSIGNED.all;entity DK_GEN_CTRL is port ( DA_CO_S : out std_logic_vector(1 downto 0 ); SECT_CON : out std_logic_vector(1 downto 0 ); E_MP1 : out std_logic; E_MP2 : out std_logic; E_MP3 : out std_logic; E_MP4 : out std_logic; E_DK1 : out std_logic; E_DK2 : out std_logic; E_DK3 : out std_logic; E_DK4 : out std_logic; CLK : in std_logic; RST : in std_logic; DE_KEY_E : in std_logic; DK32_E : out std_logic; DE_IN_E : out std_logic ); end DK_GEN_CTRL; architecture DK_GEN_CTRL of DK_GEN_CTRL is type visual_S0_states is (S0, S1, S10, S11, S12, S13, S14, S15, S16, S18, S19, S2, S21, S22, S3, S4, S5, S6, S7, S8); signal visual_S0_current : visual_S0_states; begin -- Synchronous process DK_GEN_CTRL_S0: process (CLK, RST) begin if (RST = '0') then DA_CO_S<="00"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; DK32_E<='0'; DE_IN_E<='0'; visual_S0_current <= S0; elsif (CLK'event and CLK = '1') then case visual_S0_current is when S0 => if (DE_KEY_E = '1') then DE_IN_E<='1'; visual_S0_current <= S22; else visual_S0_current <= S0; end if; when S1 => DA_CO_S<="01"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='1'; visual_S0_current <= S2; when S10 => DA_CO_S<="01"; SECT_CON<="10"; E_MP1<='0'; E_MP2<='1'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S11; when S11 => DA_CO_S<="10"; SECT_CON<="10"; E_MP1<='0'; E_MP2<='0'; E_MP3<='1'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S12; when S12 => DA_CO_S<="11"; SECT_CON<="10"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='1'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S13; when S13 => DA_CO_S<="00"; SECT_CON<="11"; E_MP1<='1'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='1'; E_DK4<='0'; visual_S0_current <= S14; when S14 => DA_CO_S<="01"; SECT_CON<="11"; E_MP1<='0'; E_MP2<='1'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S15; when S15 => DA_CO_S<="10"; SECT_CON<="11"; E_MP1<='0'; E_MP2<='0'; E_MP3<='1'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S16; when S16 => DA_CO_S<="11"; SECT_CON<="11"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='1'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S18; when S18 => DA_CO_S<="11"; SECT_CON<="11"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='1'; visual_S0_current <= S19; when S19 => E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; DK32_E<='1'; visual_S0_current <= S21; when S2 => DA_CO_S<="10"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='0'; E_MP3<='1'; visual_S0_current <= S3; when S21 => DA_CO_S<="00"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; DK32_E<='0'; DE_IN_E<='0'; visual_S0_current <= S0; when S22 => DA_CO_S<="00"; SECT_CON<="00"; E_MP1<='1'; DK32_E<='0'; DE_IN_E<='0'; visual_S0_current <= S1; when S3 => DA_CO_S<="11"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='1'; E_DK1<='0'; visual_S0_current <= S4; when S4 => DA_CO_S<="00"; SECT_CON<="01"; E_MP1<='1'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='1'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S5; when S5 => DA_CO_S<="01"; SECT_CON<="01"; E_MP1<='0'; E_MP2<='1'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S6; when S6 => DA_CO_S<="10"; SECT_CON<="01"; E_MP1<='0'; E_MP2<='0'; E_MP3<='1'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S7; when S7 => DA_CO_S<="11"; SECT_CON<="01"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='1'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S8; when S8 => DA_CO_S<="00"; SECT_CON<="10"; E_MP1<='1'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='1'; E_DK3<='0'; E_DK4<='0'; visual_S0_current <= S10; when others => DA_CO_S<="00"; SECT_CON<="00"; E_MP1<='0'; E_MP2<='0'; E_MP3<='0'; E_MP4<='0'; E_DK1<='0'; E_DK2<='0'; E_DK3<='0'; E_DK4<='0'; DK32_E<='0'; DE_IN_E<='0'; visual_S0_current <= S0; end case; end if; end process; end DK_GEN_CTRL;----------------------------------------------------
--
-- Library Name : rijndael_min_new
-- Unit Name : MPOLMUL8
-- Unit Type : Block Diagram
--
------------------------------------------------------
library ieee;use ieee.STD_LOGIC_1164.all;entity MPOLMUL8 is port ( A : in std_logic_vector(7 downto 0 ); B : in std_logic_vector(7 downto 0 ); M : in std_logic_vector(6 downto 0 ); MPOLMUL8OUT : out std_logic_vector(7 downto 0 ) ); end MPOLMUL8; architecture MPOLMUL8 of MPOLMUL8 is signal AN2_0 : std_logic_vector(7 downto 0 ); signal AN2_1 : std_logic_vector(7 downto 0 ); signal AN2_2 : std_logic_vector(7 downto 0 ); signal AN2_3 : std_logic_vector(7 downto 0 ); signal AN2_4 : std_logic_vector(7 downto 0 ); signal AN2_5 : std_logic_vector(7 downto 0 ); signal AN2_6 : std_logic_vector(7 downto 0 ); signal AN2_7 : std_logic_vector(7 downto 0 ); signal C : std_logic_vector(7 downto 0 ); signal D : std_logic_vector(7 downto 0 ); signal E : std_logic_vector(7 downto 0 ); signal F : std_logic_vector(7 downto 0 ); signal G : std_logic_vector(7 downto 0 ); signal H : std_logic_vector(7 downto 0 ); signal I : std_logic_vector(7 downto 0 ); signal J : std_logic_vector(7 downto 0 ); signal K : std_logic_vector(7 downto 0 ); signal L : std_logic_vector(7 downto 0 ); signal N : std_logic_vector(7 downto 0 ); signal P : std_logic_vector(7 downto 0 ); signal Q : std_logic_vector(7 downto 0 ); signal R : std_logic_vector(7 downto 0 ); signal S0 : std_logic_vector(7 downto 0 ); signal S1 : std_logic_vector(7 downto 0 ); signal S2 : std_logic_vector(7 downto 0 ); signal S3 : std_logic_vector(7 downto 0 ); signal S4 : std_logic_vector(7 downto 0 ); signal S5 : std_logic_vector(7 downto 0 ); signal S6 : std_logic_vector(7 downto 0 ); signal S7 : std_logic_vector(7 downto 0 ); signal T_0 : std_logic_vector(7 downto 0 ); signal T_1 : std_logic_vector(7 downto 0 ); signal T_2 : std_logic_vector(7 downto 0 ); signal T_3 : std_logic_vector(7 downto 0 ); signal T_4 : std_logic_vector(7 downto 0 ); signal T_5 : std_logic_vector(7 downto 0 ); signal VCC : std_logic; signal VSS : std_logic; signal XORD1_1 : std_logic_vector(7 downto 0 ); signal XORD_0 : std_logic_vector(7 downto 0 ); signal XORD_1 : std_logic_vector(7 downto 0 ); signal XORD_2 : std_logic_vector(7 downto 0 ); signal XORD_3 : std_logic_vector(7 downto 0 ); signal XORD_4 : std_logic_vector(7 downto 0 ); signal XORD_5 : std_logic_vector(7 downto 0 ); signal XORD_6 : std_logic_vector(7 downto 0 ); signal visual_MUX21_8_0_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C8_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C10_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C14_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C16_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C20_O : std_logic_vector(8 - 1 downto 0 ); signal visual_C22_O : std_logic_vector(8 - 1 downto 0 ); begin C(7 downto 0) <= ( XORD_0(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_0(7 downto 1) <= B(6 downto 0); XORD_0(0) <= VSS; VSS <= '0'; XORD_1(7 downto 1) <= M(6 downto 0); XORD_1(0) <= VCC; VCC <= '1'; D(7 downto 0) <= (visual_MUX21_8_0_O); process (XORD_0 , C , B) begin case B(7) is when '0' => visual_MUX21_8_0_O <= XORD_0(7 downto 0); when others => visual_MUX21_8_0_O <= C(7 downto 0); end case; end process; E(7 downto 0) <= ( XORD1_1(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD1_1(7 downto 1) <= D(6 downto 0); XORD1_1(0) <= VSS; F(7 downto 0) <= (visual_C8_O); process (XORD1_1 , E , D) begin case D(7) is when '0' => visual_C8_O <= XORD1_1(7 downto 0); when others => visual_C8_O <= E(7 downto 0); end case; end process; G(7 downto 0) <= ( XORD_2(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_2(7 downto 1) <= F(6 downto 0); XORD_2(0) <= VSS; H(7 downto 0) <= (visual_C10_O); process (XORD_2 , G , F) begin case F(7) is when '0' => visual_C10_O <= XORD_2(7 downto 0); when others => visual_C10_O <= G(7 downto 0); end case; end process; I(7 downto 0) <= ( XORD_3(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_3(7 downto 1) <= H(6 downto 0); XORD_3(0) <= VSS; J(7 downto 0) <= (visual_C14_O); process (XORD_3 , I , H) begin case H(7) is when '0' => visual_C14_O <= XORD_3(7 downto 0); when others => visual_C14_O <= I(7 downto 0); end case; end process; K(7 downto 0) <= ( XORD_4(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_4(7 downto 1) <= J(6 downto 0); XORD_4(0) <= VSS; L(7 downto 0) <= (visual_C16_O); process (XORD_4 , K , J) begin case J(7) is when '0' => visual_C16_O <= XORD_4(7 downto 0); when others => visual_C16_O <= K(7 downto 0); end case; end process; N(7 downto 0) <= ( XORD_5(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_5(7 downto 1) <= L(6 downto 0); XORD_5(0) <= VSS; P(7 downto 0) <= (visual_C20_O); process (XORD_5 , N , L) begin case L(7) is when '0' => visual_C20_O <= XORD_5(7 downto 0); when others => visual_C20_O <= N(7 downto 0); end case; end process; Q(7 downto 0) <= ( XORD_6(7 downto 0)) xor ( XORD_1(7 downto 0)); XORD_6(7 downto 1) <= P(6 downto 0); XORD_6(0) <= VSS; R(7 downto 0) <= (visual_C22_O); process (XORD_6 , Q , P) begin?? 快捷鍵說明
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