[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=0
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1

[Document1]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Texas Instruments\TI Logic Gate 2.IntLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document2]
DocumentPath=C:\Program Files\Altium Designer Winter 09\Library\Texas Instruments\TI Logic Flip-Flop.IntLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document3]
DocumentPath=二進制計數器.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Document4]
DocumentPath=二進制計數器.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None

[Generic_SignalIntegritySimulation]
SignalIntegrityInitialised=-1
TrackImpedance=100
TrackLength=20000000
UseManhattan=0
UseSupplyNetsRules=-1
SupplyNetsCount=0
UseStimulusRules=-1
StimKind=1
StimLevel=0
StimStartTime=1E-8
StimStopTime=6E-8
StimPeriodTime=1E-7

[Generic_SignalIntegrityPanelSetup]
TerminationName0=No Termination
TerminationEnabled0=True
TerminationSweeps0=1
TerminationName1=Serial Res
TerminationEnabled1=False
TerminationSweeps1=10
TerminationName2=Parallel Res to VCC
TerminationEnabled2=False
TerminationSweeps2=10
TerminationName3=Parallel Res to GND
TerminationEnabled3=False
TerminationSweeps3=10
TerminationName4=Parallel Res to VCC & GND
TerminationEnabled4=False
TerminationSweeps4=10
TerminationName5=Parallel Cap to GND
TerminationEnabled5=False
TerminationSweeps5=10
TerminationName6=Res and Cap to GND
TerminationEnabled6=False
TerminationSweeps6=10
TerminationName7=Parallel Schottky Diodes
TerminationEnabled7=False
TerminationSweeps7=10
TerminationMinR10=0
TerminationMaxR10=0
TerminationPrefR10=0
TerminationMinR20=0
TerminationMaxR20=0
TerminationPrefR20=0
TerminationMinC0=0
TerminationMaxC0=0
TerminationPrefC0=0
TerminationVCC0=0
TerminationMinR11=25
TerminationMaxR11=150
TerminationPrefR11=47
TerminationMinR21=0
TerminationMaxR21=0
TerminationPrefR21=0
TerminationMinC1=0
TerminationMaxC1=0
TerminationPrefC1=0
TerminationVCC1=0
TerminationMinR12=50
TerminationMaxR12=200
TerminationPrefR12=100
TerminationMinR22=0
TerminationMaxR22=0
TerminationPrefR22=0
TerminationMinC2=0
TerminationMaxC2=0
TerminationPrefC2=0
TerminationVCC2=5
TerminationMinR13=0
TerminationMaxR13=0
TerminationPrefR13=0
TerminationMinR23=50
TerminationMaxR23=200
TerminationPrefR23=100
TerminationMinC3=0
TerminationMaxC3=0
TerminationPrefC3=0
TerminationVCC3=0
TerminationMinR14=50
TerminationMaxR14=200
TerminationPrefR14=100
TerminationMinR24=50
TerminationMaxR24=200
TerminationPrefR24=100
TerminationMinC4=0
TerminationMaxC4=0
TerminationPrefC4=0
TerminationVCC4=5
TerminationMinR15=0
TerminationMaxR15=0
TerminationPrefR15=0
TerminationMinR25=0
TerminationMaxR25=0
TerminationPrefR25=0
TerminationMinC5=2.35E-11
TerminationMaxC5=9.4E-11
TerminationPrefC5=4.7E-11
TerminationVCC5=0
TerminationMinR16=0
TerminationMaxR16=0
TerminationPrefR16=0
TerminationMinR26=34
TerminationMaxR26=136
TerminationPrefR26=68
TerminationMinC6=5E-11
TerminationMaxC6=2E-10
TerminationPrefC6=1E-10
TerminationVCC6=0
TerminationMinR17=0
TerminationMaxR17=0
TerminationPrefR17=0
TerminationMinR27=0
TerminationMaxR27=0
TerminationPrefR27=0
TerminationMinC7=0
TerminationMaxC7=0
TerminationPrefC7=0
TerminationVCC7=5

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Microsoft XPS Document Writer
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=CadnetixNetlist
OutputName1=Cadnetix Netlist
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=CalayNetlist
OutputName2=Calay Netlist
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=EDIF
OutputName3=EDIF for PCB
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=EESofNetlist
OutputName4=EESof Netlist
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=IntergraphNetlist
OutputName5=Intergraph Netlist
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=MentorBoardStationNetlist
OutputName6=Mentor BoardStation Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=MultiWire
OutputName7=MultiWire
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=OrCadPCB2Netlist
OutputName8=Orcad/PCB2 Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=PADSNetlist
OutputName9=PADS ASCII Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=Pcad
OutputName10=Pcad for PCB
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=PCADNetlist
OutputName11=PCAD Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=PCADnltNetlist
OutputName12=PCADnlt Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Protel2Netlist
OutputName13=Protel2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=ProtelNetlist
OutputName14=Protel
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=RacalNetlist
OutputName15=Racal Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=RINFNetlist
OutputName16=RINF Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SciCardsNetlist
OutputName17=SciCards Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SIMetrixNetlist
OutputName18=SIMetrix
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=SIMPLISNetlist
OutputName19=SIMPLIS
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=TangoNetlist
OutputName20=Tango Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=TelesisNetlist
OutputName21=Telesis Netlist
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=Verilog
OutputName22=Verilog File
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=VHDL
OutputName23=VHDL File
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=WireListNetlist
OutputName24=WireList Netlist
OutputDocumentPath24=