(edif Test1_PrjFpg
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
     (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2010 5 27 11 21 5)
      (program "Altium Designer - EDIF For PCB"
        (version "1.0.0")
      )
      (author "EDIF For PCB")
    )
  )

  (library COMPONENT_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell AND2N1S
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O  (direction OUTPUT))
        )
      )
    )
    (cell NOR2N1S
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O  (direction OUTPUT))
        )
      )
    )
    (cell NOR2S
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O  (direction OUTPUT))
        )
      )
    )
  )
  (library SHEET_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell Test1_SchDoc
      (cellType generic)
      (view netListView
        (viewType netlist)
        (interface
        )
        (contents
          (Instance U1
            (viewRef NetlistView
              (cellRef AND2N1S
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property ArchiveName (String "GENERIC" ))
            (Property Comment (String "AND2N1S" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Core &Resource Usage" ))
            (Property ComponentLink1URL (String "CR0136 FPGA Logic Primitive Resource Usage.pdf#page=10" ))
            (Property Description (String "2-Input AND Gate with Active Low A Input, Single Pin Version" ))
            (Property Footprint (String "" ))
            (Property FunctionalClass (String "Logic Primitive" ))
            (Property HelpURL (String "CR0118 FPGA Generic Library Guide.pdf#page=114" ))
            (Property LastRevisionNo (String "1.00.00" ))
            (Property (rename Library_Name "Library Name") (String "FPGA Generic.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "AND2N1S" ))
            (Property PCB3D (String "" ))
            (Property PortSize (String "2" ))
            (Property PortStyle (String "Single Pin Version" ))
            (Property Published (String "29-Jan-2004" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property SubClass (String "AND" ))
            (Property VHDLIB_SIM (String "GENERIC_LIB" ))
            (Property XilinxEquivalent (String "AND2B1" ))
            (Property Description (String "2-Input AND Gate with Active Low A Input, Single Pin Version" ))
            (Property UniqueId (String "\PDPWETJO" ))
            (Property PhysicalPath (String "Test1" ))
            (Property ChannelOffset (String "0" ))
          )
          (Instance U2
            (viewRef NetlistView
              (cellRef NOR2S
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property ArchiveName (String "GENERIC" ))
            (Property Comment (String "NOR2S" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Core &Resource Usage" ))
            (Property ComponentLink1URL (String "CR0136 FPGA Logic Primitive Resource Usage.pdf#page=139" ))
            (Property Description (String "2-Input NOR Gate, Single Pin Version" ))
            (Property Footprint (String "" ))
            (Property FunctionalClass (String "Logic Primitive" ))
            (Property HelpURL (String "CR0118 FPGA Generic Library Guide.pdf#page=406" ))
            (Property LastRevisionNo (String "1.00.00" ))
            (Property (rename Library_Name "Library Name") (String "FPGA Generic.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "NOR2S" ))
            (Property PCB3D (String "" ))
            (Property PortSize (String "2" ))
            (Property PortStyle (String "Single Pin Version" ))
            (Property Published (String "29-Jan-2004" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property SubClass (String "NOR" ))
            (Property VHDLIB_SIM (String "GENERIC_LIB" ))
            (Property XilinxEquivalent (String "NOR2" ))
            (Property Description (String "2-Input NOR Gate, Single Pin Version" ))
            (Property UniqueId (String "\USIJPCWV" ))
            (Property PhysicalPath (String "Test1" ))
            (Property ChannelOffset (String "1" ))
          )
          (Instance U3
            (viewRef NetlistView
              (cellRef NOR2N1S
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property ArchiveName (String "GENERIC" ))
            (Property Comment (String "NOR2N1S" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property ComponentLink1Description (String "Core &Resource Usage" ))
            (Property ComponentLink1URL (String "CR0136 FPGA Logic Primitive Resource Usage.pdf#page=136" ))
            (Property Description (String "2-Input NOR Gate with Active Low A Input, Single Pin Version" ))
            (Property Footprint (String "" ))
            (Property FunctionalClass (String "Logic Primitive" ))
            (Property HelpURL (String "CR0118 FPGA Generic Library Guide.pdf#page=406" ))
            (Property LastRevisionNo (String "1.00.00" ))
            (Property (rename Library_Name "Library Name") (String "FPGA Generic.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "NOR2N1S" ))
            (Property PCB3D (String "" ))
            (Property PortSize (String "2" ))
            (Property PortStyle (String "Single Pin Version" ))
            (Property Published (String "29-Jan-2004" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property SubClass (String "NOR" ))
            (Property VHDLIB_SIM (String "GENERIC_LIB" ))
            (Property XilinxEquivalent (String "NOR2B1" ))
            (Property Description (String "2-Input NOR Gate with Active Low A Input, Single Pin Version" ))
            (Property UniqueId (String "\BAVGHIND" ))
            (Property PhysicalPath (String "Test1" ))
            (Property ChannelOffset (String "2" ))
          )
          (Net NetU1_I0
            (Joined 
                (PortRef I0 (InstanceRef U1))
            )
          )
          (Net NetU1_I1
            (Joined 
                (PortRef I1 (InstanceRef U1))
            )
          )
          (Net NetU1_O
            (Joined 
                (PortRef O (InstanceRef U1))
                (PortRef I0 (InstanceRef U3))
            )
          )
          (Net NetU2_I0
            (Joined 
                (PortRef I0 (InstanceRef U2))
            )
          )
          (Net NetU2_I1
            (Joined 
                (PortRef I1 (InstanceRef U2))
            )
          )
          (Net NetU3_O
            (Joined 
                (PortRef O (InstanceRef U3))
            )
          )
       )
     )
   )
  )
  (design Test1_PrjFpg
    (cellRef Test1_SchDoc
      (libraryRef SHEET_LIB)
    )
  )
)