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-- VHDL Testbench for fpga_project1
-- 2010 5 27 17 30 46
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
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Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     IEEE.std_logic_textio.all;
Use     STD.textio.all;
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entity Testfpga_project1 is
end Testfpga_project1;
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architecture stimulus of Testfpga_project1 is
    file RESULTS: TEXT open WRITE_MODE is "results.txt";
    procedure WRITE_RESULTS(
    ) is
        variable l_out : line;
    begin
        write(l_out, now, right, 15);
        writeline(RESULTS, l_out);
    end procedure;

    component fpga_project1
        port (
        );
    end component;


begin
    DUT:fpga_project1 port map (
    );

    STIMULUS0:process
    begin
        -- insert stimulus here
        wait;
    end process;

    WRITE_RESULTS(
    );

end architecture;
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