?? multi_1.vhd
字號:
library ieee; --1位乘法器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity multi_1 is
port(m1_x:in std_logic;
m1_y:in std_logic_vector(7 downto 0);
m1_out:out std_logic_vector(7 downto 0));
end multi_1;
architecture arc_multi_1 of multi_1 is
begin
process(m1_x,m1_y)
begin
if m1_x='1' then m1_out<=m1_y;
else m1_out<="00000000";
end if;
end process;
end arc_multi_1;
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