#define PRISM2_PLX/* Host AP driver's support for PC Cards on PCI adapters using PLX9052 is * based on: * - Host AP driver patch from james@madingley.org * - linux-wlan-ng driver, Copyright (C) AbsoluteValue Systems, Inc. */#include <linux/module.h>#include <linux/init.h>#include <linux/if.h>#include <linux/skbuff.h>#include <linux/netdevice.h>#include <linux/workqueue.h>#include <linux/wireless.h>#include <net/iw_handler.h>#include <linux/ioport.h>#include <linux/pci.h>#include <asm/io.h>#include "hostap_wlan.h"static char *dev_info = "hostap_plx";MODULE_AUTHOR("Jouni Malinen");MODULE_DESCRIPTION("Support for Intersil Prism2-based 802.11 wireless LAN "		   "cards (PLX).");MODULE_SUPPORTED_DEVICE("Intersil Prism2-based WLAN cards (PLX)");MODULE_LICENSE("GPL");static int ignore_cis;module_param(ignore_cis, int, 0444);MODULE_PARM_DESC(ignore_cis, "Do not verify manfid information in CIS");/* struct local_info::hw_priv */struct hostap_plx_priv {	void __iomem *attr_mem;	unsigned int cor_offset;};#define PLX_MIN_ATTR_LEN 512	/* at least 2 x 256 is needed for CIS */#define COR_SRESET       0x80#define COR_LEVLREQ      0x40#define COR_ENABLE_FUNC  0x01/* PCI Configuration Registers */#define PLX_PCIIPR       0x3d   /* PCI Interrupt Pin *//* Local Configuration Registers */#define PLX_INTCSR       0x4c   /* Interrupt Control/Status Register */#define PLX_INTCSR_PCI_INTEN BIT(6) /* PCI Interrupt Enable */#define PLX_CNTRL        0x50#define PLX_CNTRL_SERIAL_EEPROM_PRESENT BIT(28)#define PLXDEV(vendor,dev,str) { vendor, dev, PCI_ANY_ID, PCI_ANY_ID }static struct pci_device_id prism2_plx_id_table[] __devinitdata = {	PLXDEV(0x10b7, 0x7770, "3Com AirConnect PCI 777A"),	PLXDEV(0x111a, 0x1023, "Siemens SpeedStream SS1023"),	PLXDEV(0x126c, 0x8030, "Nortel emobility"),	PLXDEV(0x1562, 0x0001, "Symbol LA-4123"),	PLXDEV(0x1385, 0x4100, "Netgear MA301"),	PLXDEV(0x15e8, 0x0130, "National Datacomm NCP130 (PLX9052)"),	PLXDEV(0x15e8, 0x0131, "National Datacomm NCP130 (TMD7160)"),	PLXDEV(0x1638, 0x1100, "Eumitcom WL11000"),	PLXDEV(0x16ab, 0x1100, "Global Sun Tech GL24110P"),	PLXDEV(0x16ab, 0x1101, "Global Sun Tech GL24110P (?)"),	PLXDEV(0x16ab, 0x1102, "Linksys WPC11 with WDT11"),	PLXDEV(0x16ab, 0x1103, "Longshine 8031"),	PLXDEV(0x16ec, 0x3685, "US Robotics USR2415"),	PLXDEV(0xec80, 0xec00, "Belkin F5D6000"),	{ 0 }};/* Array of known Prism2/2.5 PC Card manufactured ids. If your card's manfid * is not listed here, you will need to add it here to get the driver * initialized. */static struct prism2_plx_manfid {	u16 manfid1, manfid2;} prism2_plx_known_manfids[] = {	{ 0x000b, 0x7110 } /* D-Link DWL-650 Rev. P1 */,	{ 0x000b, 0x7300 } /* Philips 802.11b WLAN PCMCIA */,	{ 0x0101, 0x0777 } /* 3Com AirConnect PCI 777A */,	{ 0x0126, 0x8000 } /* Proxim RangeLAN */,	{ 0x0138, 0x0002 } /* Compaq WL100 */,	{ 0x0156, 0x0002 } /* Intersil Prism II Ref. Design (and others) */,	{ 0x026f, 0x030b } /* Buffalo WLI-CF-S11G */,	{ 0x0274, 0x1612 } /* Linksys WPC11 Ver 2.5 */,	{ 0x0274, 0x1613 } /* Linksys WPC11 Ver 3 */,	{ 0x028a, 0x0002 } /* D-Link DRC-650 */,	{ 0x0250, 0x0002 } /* Samsung SWL2000-N */,	{ 0xc250, 0x0002 } /* EMTAC A2424i */,	{ 0xd601, 0x0002 } /* Z-Com XI300 */,	{ 0xd601, 0x0005 } /* Zcomax XI-325H 200mW */,	{ 0, 0}};#ifdef PRISM2_IO_DEBUGstatic inline void hfa384x_outb_debug(struct net_device *dev, int a, u8 v){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_OUTB, a, v);	outb(v, dev->base_addr + a);	spin_unlock_irqrestore(&local->lock, flags);}static inline u8 hfa384x_inb_debug(struct net_device *dev, int a){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	u8 v;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	v = inb(dev->base_addr + a);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_INB, a, v);	spin_unlock_irqrestore(&local->lock, flags);	return v;}static inline void hfa384x_outw_debug(struct net_device *dev, int a, u16 v){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_OUTW, a, v);	outw(v, dev->base_addr + a);	spin_unlock_irqrestore(&local->lock, flags);}static inline u16 hfa384x_inw_debug(struct net_device *dev, int a){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	u16 v;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	v = inw(dev->base_addr + a);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_INW, a, v);	spin_unlock_irqrestore(&local->lock, flags);	return v;}static inline void hfa384x_outsw_debug(struct net_device *dev, int a,				       u8 *buf, int wc){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_OUTSW, a, wc);	outsw(dev->base_addr + a, buf, wc);	spin_unlock_irqrestore(&local->lock, flags);}static inline void hfa384x_insw_debug(struct net_device *dev, int a,				      u8 *buf, int wc){	struct hostap_interface *iface;	local_info_t *local;	unsigned long flags;	iface = netdev_priv(dev);	local = iface->local;	spin_lock_irqsave(&local->lock, flags);	prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_INSW, a, wc);	insw(dev->base_addr + a, buf, wc);	spin_unlock_irqrestore(&local->lock, flags);}#define HFA384X_OUTB(v,a) hfa384x_outb_debug(dev, (a), (v))#define HFA384X_INB(a) hfa384x_inb_debug(dev, (a))#define HFA384X_OUTW(v,a) hfa384x_outw_debug(dev, (a), (v))#define HFA384X_INW(a) hfa384x_inw_debug(dev, (a))#define HFA384X_OUTSW(a, buf, wc) hfa384x_outsw_debug(dev, (a), (buf), (wc))#define HFA384X_INSW(a, buf, wc) hfa384x_insw_debug(dev, (a), (buf), (wc))#else /* PRISM2_IO_DEBUG */#define HFA384X_OUTB(v,a) outb((v), dev->base_addr + (a))#define HFA384X_INB(a) inb(dev->base_addr + (a))#define HFA384X_OUTW(v,a) outw((v), dev->base_addr + (a))#define HFA384X_INW(a) inw(dev->base_addr + (a))#define HFA384X_INSW(a, buf, wc) insw(dev->base_addr + (a), buf, wc)#define HFA384X_OUTSW(a, buf, wc) outsw(dev->base_addr + (a), buf, wc)#endif /* PRISM2_IO_DEBUG */static int hfa384x_from_bap(struct net_device *dev, u16 bap, void *buf,			    int len){	u16 d_off;	u16 *pos;	d_off = (bap == 1) ? HFA384X_DATA1_OFF : HFA384X_DATA0_OFF;	pos = (u16 *) buf;	if (len / 2)		HFA384X_INSW(d_off, buf, len / 2);	pos += len / 2;	if (len & 1)		*((char *) pos) = HFA384X_INB(d_off);	return 0;}static int hfa384x_to_bap(struct net_device *dev, u16 bap, void *buf, int len){	u16 d_off;	u16 *pos;	d_off = (bap == 1) ? HFA384X_DATA1_OFF : HFA384X_DATA0_OFF;	pos = (u16 *) buf;	if (len / 2)		HFA384X_OUTSW(d_off, buf, len / 2);	pos += len / 2;	if (len & 1)		HFA384X_OUTB(*((char *) pos), d_off);	return 0;}/* FIX: This might change at some point.. */#include "hostap_hw.c"static void prism2_plx_cor_sreset(local_info_t *local){	unsigned char corsave;	struct hostap_plx_priv *hw_priv = local->hw_priv;	printk(KERN_DEBUG "%s: Doing reset via direct COR access.\n",	       dev_info);	/* Set sreset bit of COR and clear it after hold time */	if (hw_priv->attr_mem == NULL) {		/* TMD7160 - COR at card's first I/O addr */		corsave = inb(hw_priv->cor_offset);		outb(corsave | COR_SRESET, hw_priv->cor_offset);		mdelay(2);		outb(corsave & ~COR_SRESET, hw_priv->cor_offset);		mdelay(2);	} else {		/* PLX9052 */		corsave = readb(hw_priv->attr_mem + hw_priv->cor_offset);		writeb(corsave | COR_SRESET,		       hw_priv->attr_mem + hw_priv->cor_offset);		mdelay(2);		writeb(corsave & ~COR_SRESET,		       hw_priv->attr_mem + hw_priv->cor_offset);		mdelay(2);	}}static void prism2_plx_genesis_reset(local_info_t *local, int hcr){	unsigned char corsave;	struct hostap_plx_priv *hw_priv = local->hw_priv;	if (hw_priv->attr_mem == NULL) {		/* TMD7160 - COR at card's first I/O addr */		corsave = inb(hw_priv->cor_offset);		outb(corsave | COR_SRESET, hw_priv->cor_offset);		mdelay(10);		outb(hcr, hw_priv->cor_offset + 2);		mdelay(10);		outb(corsave & ~COR_SRESET, hw_priv->cor_offset);		mdelay(10);	} else {		/* PLX9052 */		corsave = readb(hw_priv->attr_mem + hw_priv->cor_offset);		writeb(corsave | COR_SRESET,		       hw_priv->attr_mem + hw_priv->cor_offset);		mdelay(10);		writeb(hcr, hw_priv->attr_mem + hw_priv->cor_offset + 2);		mdelay(10);