//
// Copyright (c) Marvell Taiwan Corporation.  All rights reserved.
//
//
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

pxa-gspi.h

Abstract:

Interface of SSP Host Controller

Notes: 

	Modified from %SystemRoot%\WINCE500\PUBLIC\COMMON\OAK\DRIVERS\SERIAL\SER_CARD\ser_card.h

--*/
#ifndef __PXA_GSPI_H__
#define __PXA_GSPI_H__

#ifdef __cplusplus
extern "C" {
#endif

//#include <windows.h>  //JKU
#include <nkintr.h>
#include <ceddk.h>
#include <bulverde.h>
#include "pxa-ssp.h"
#include "pxa-dma.h"
#include "myintr.h"


#define		MVL_DEF_DRR			0x05
#define		MVL_DEF_DRP			0x0e
#define     GSPI_BUS_CLK_RATE   13000000
typedef enum {
	RDDMA_PARAM = 0,
	WTDMA_PARAM,
	MAXDMA_PARAM
};

typedef enum {
	GSPI_SUCCESS,
	GSPI_TIMEOUT,
	GSPI_INVALIDARGS,
	GSPI_MAX
} GSPI_STATUS;


typedef		int (*ISRFUNC)		(void* isrContext);

///PXA270 SSP Hardwar Context
typedef struct _SSP_HARDWARE_CONTEXT {
	volatile BULVERDE_GPIO_REG		*pGPIORegs;
	volatile BULVERDE_SSP_EXT_REG	*pSSPRegs;
	volatile BULVERDE_CLKMGR_REG	*pCLKRegs;
	volatile BULVERDE_DMA_REG		*pDMARegs;
	volatile BULVERDE_OST_REG		*pOSTRegs;

	CRITICAL_SECTION				SSPCrit;

	///DMA Descriptors
	volatile DMADescriptorChannelType *read_desc;				// virtual address of DMA descriptor
    volatile DMADescriptorChannelType *read_desc_phys_addr;		// physical address of DMA descriptor

	volatile DMADescriptorChannelType *write_desc;				// virtual address of DMA descriptor
    volatile DMADescriptorChannelType *write_desc_phys_addr;	// physical address of DMA descriptor

	volatile DMADescriptorChannelType *rw_desc;					// virtual address of DMA descriptor
    volatile DMADescriptorChannelType *rw_desc_phys_addr;		// physical address of DMA descriptor

	///Interrupt
	DWORD				dwIRQ;								/// IRQ value
	DWORD				dwSysIntr;							/// SYSINTR value
	HANDLE				hIntrHandle;						/// Handle to Interrupt event.
	HANDLE				hIntrThread;						/// Handle to thread which waits on

	HANDLE				hGIIsr;								/// GIISR


	///DMA Buffers
	volatile PBYTE		iodata;								/// virtual address of DMA buffer (R/W)
	volatile PBYTE		phys_addr;							/// physical address of DMA buffer
	volatile PBYTE		iorw;								/// virtual address of DMA buffer (dummy_write)
	volatile PBYTE		phys_addr_rw;						/// physical address of DMA buffer

	///DMA Interrupt
/*
	DWORD				dwDmaIRQ;							/// DMA IRQ value
	DWORD				dwDmaSysIntr;						/// DMA SYSINTR value

	HANDLE				hDMAIntrHandle;						/// Handle to Interrupt event.
	HANDLE				hDMAIntrThread;						/// Handle to thread which waits on
															///		an interrupt event.
*/
	///Bus-Access handle: for ISR
	HANDLE				hBusAcceHND;
	///LPCTSTR				pszActiveKey;

	MYDMAPARAM			DMAParam[MAXDMA_PARAM];				///DMA parameter (2 channels for both read/write)
	MYINTRINFO			DMAIntrInfo[MAXDMA_PARAM];			///DMA Interrupt Info

	MYINTRINFO			DevIntrInfo;						///Device Interrupt Info

	///DMA channel
	///DWORD				chan;							///Read Channel
	///DWORD				chanrw;							///Write Channel

	///Bus-Access handle: for ISR
	///HANDLE				hBusAccessHandle;
	///LPCTSTR				pszActiveKey;

	///DMA ISR handler DLL name
	TCHAR				wszDmaIsrDll[1024];
	///DMA ISR handler function name
	TCHAR				wszDmaIsrHandler[256];

	///HANDLE				hDMAIsrHandler;					///handle to DMA ISR handler
	///HANDLE				hDMAInterruptEvent;				///DMA interrupt event
	///DWORD				DmaIstThreadPriority;			///DMA IST thread priority
	///HANDLE				hDmaInterruptThread;			///handle to the DMA IST thread
	
	/// ISR Callback routine
	HANDLE				isrContext;
	ISRFUNC				isrFunc;

	///Synchronization Semaphore 
	HANDLE				waitqueue;

	BOOL				DriverShutdown;

} SSP_HARDWARE_CONTEXT, *PSSP_HARDWARE_CONTEXT;

///PXA270 SSP OpenContext
typedef struct _SSP_OPEN_CONTEXT {
	PSSP_HARDWARE_CONTEXT	pHC;
} SSP_OPEN_CONTEXT, *PSSP_OPEN_CONTEXT;

void udelay(volatile BULVERDE_OST_REG *pOstRegs, DWORD ms);

PVOID pxa_gspi_Init(void);
DWORD pxa_gspi_register_isr(PVOID ssphc, void* Adapter, ISRFUNC isrFunc);
BOOL gspx_read_reg8(PVOID hDC, WORD reg, BYTE *data);

#if 0  //JKU: moved to JaguarGSPX.h
PVOID gspx_init(void *pSpiParam);
BOOL gspx_deinit(PVOID hDC);
///GSPI_STATUS ssp_read_register(PVOID hDC, WORD regaddr, WORD* regdatPt);
//GSPI_STATUS ssp_read_register(PVOID hDC, WORD* regdatPt, WORD regaddr);
//GSPI_STATUS ssp_write_register(PVOID hDC, WORD regaddr, WORD* regdatPt);

//GSPI_STATUS ssp_write_data(PVOID hDC, WORD* datPt, WORD reg, WORD nword);
//GSPI_STATUS ssp_read_data(PVOID hDC, WORD* datPt, WORD reg, WORD nword);
BOOL pxa_gspi_Deinit(PVOID hDC);
BOOL gspx_read_reg16(PVOID hDC, WORD reg, WORD *data);
BOOL gspx_read_reg32(PVOID hDC, UINT16 reg, UINT32 *data);
BOOL gspx_read_mem(PVOID hDC,UINT16 reg, UINT16 nword, UINT16* datPt);
BOOL gspx_write_reg16(PVOID hDC, WORD regaddr, WORD regdata);
BOOL gspx_write_mem(PVOID hDC,WORD regaddr, WORD nword, WORD* datPt);
#endif

//JKU: int gspx_set_callback(PVOID pHC, PVOID cb, void *data);


#ifdef __cplusplus
}
#endif
#endif __PXA_GSPI_H__