/*
File name: pxa-gpio.h
Description: This is an utility for configuring the Bulverde GPIO
	- We implemented it based on the Monta_Vista generic.c
*/
#ifndef _PXA_GPIO_H
#define _PXA_GPIO_H
#if __cplusplus
extern "C" 
{
#endif

/* GPIO alternate function mode & direction */
#define GPIO_IN			0x000
#define GPIO_OUT		0x080
#define GPIO_ALT_FN_1_IN	0x100
#define GPIO_ALT_FN_1_OUT	0x180
#define GPIO_ALT_FN_2_IN	0x200
#define GPIO_ALT_FN_2_OUT	0x280
#define GPIO_ALT_FN_3_IN	0x300
#define GPIO_ALT_FN_3_OUT	0x380
#define GPIO_MD_MASK_NR		0x07f
#define GPIO_MD_MASK_DIR	0x080
#define GPIO_MD_MASK_FN		0x300


#define _GPLR0_(x)		(&x->GPLR0)  /* GPIO Pin-Level Register GPIO<31:0> */
#define _GPDR0_(x)		(&x->GPDR0)  /* GPIO Pin Direction Register GPIO<31:0> */
#define _GPSR0_(x)		(&x->GPSR0)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define _GPCR0_(x)		(&x->GPCR0)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define _GRER0_(x)		(&x->GRER0)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define _GFER0_(x)		(&x->GFER0)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define _GEDR0_(x)		(&x->GEDR0)  /* GPIO Edge Detect Status Register GPIO<31:0> */

#define _GPLR1_(x)		(&x->GPLR1)  /* GPIO Pin-Level Register GPIO<63:32> */
#define _GPDR1_(x)		(&x->GPDR1)  /* GPIO Pin Direction Register GPIO<63:32> */
#define _GPSR1_(x)		(&x->GPSR1)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define _GPCR1_(x)		(&x->GPCR1)  /* GPIO Pin Output Clear Register GPIO<63:32> */
#define _GRER1_(x)		(&x->GRER1)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define _GFER1_(x)		(&x->GFER1)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define _GEDR1_(x)		(&x->GEDR1)  /* GPIO Edge Detect Status Register GPIO<63:32> */

#define _GPLR2_(x)		(&x->GPLR2)  /* GPIO Pin-Level Register GPIO<95:64> */
#define _GPDR2_(x)		(&x->GPDR2)  /* GPIO Pin Direction Register GPIO<95:64> */
#define _GPSR2_(x)		(&x->GPSR2)  /* GPIO Pin Output Set Register GPIO<95:64> */
#define _GPCR2_(x)		(&x->GPCR2)  /* GPIO Pin Output Clear Register GPIO<95:64> */
#define _GRER2_(x)		(&x->GRER2)  /* GPIO Rising-Edge Detect Register GPIO<95:64> */
#define _GFER2_(x)		(&x->GFER2)  /* GPIO Falling-Edge Detect Register GPIO<95:64> */
#define _GEDR2_(x)		(&x->GEDR2)  /* GPIO Edge Detect Status Register GPIO<95:64> */

#define _GPLR3_(x)		(&x->GPLR3)  /* GPIO Pin-Level Register GPIO<127:96> */
#define _GPDR3_(x)		(&x->GPDR3)  /* GPIO Pin Direction Register GPIO<127:96> */
#define _GPSR3_(x)		(&x->GPSR3)  /* GPIO Pin Output Set Register GPIO<127:96> */
#define _GPCR3_(x)		(&x->GPCR3)  /* GPIO Pin Output Clear Register GPIO<127:96> */
#define _GRER3_(x)		(&x->GRER3)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
#define _GFER3_(x)		(&x->GFER3)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
#define _GEDR3_(x)		(&x->GEDR3)  /* GPIO Edge Detect Status Register GPIO<127:96> */


#define GPIO_bit(x)	(1 << ((x) & 0x1f))

#define _3GPLR(a, x)		_GPLR0_(a)
#define _3GPDR(a, x)		_GPDR0_(a)
#define _3GPSR(a, x)		_GPSR0_(a)
#define _3GPCR(a, x)		_GPCR0_(a)
#define _3GRER(a, x)		_GRER0_(a)
#define _3GFER(a, x)		_GFER0_(a)
#define _3GEDR(a, x)		_GEDR0_(a)

#define _2GPLR(a, x)		((((x) & 0x7f) < 32) ? _3GPLR(a, x) : _GPLR1_(a))
#define _2GPDR(a, x)		((((x) & 0x7f) < 32) ? _3GPDR(a, x) : _GPDR1_(a))
#define _2GPSR(a, x)		((((x) & 0x7f) < 32) ? _3GPSR(a, x) : _GPSR1_(a))
#define _2GPCR(a, x)		((((x) & 0x7f) < 32) ? _3GPCR(a, x) : _GPCR1_(a))
#define _2GRER(a, x)		((((x) & 0x7f) < 32) ? _3GRER(a, x) : _GRER1_(a))
#define _2GFER(a, x)		((((x) & 0x7f) < 32) ? _3GFER(a, x) : _GFER1_(a))
#define _2GEDR(a, x)		((((x) & 0x7f) < 32) ? _3GEDR(a, x) : _GEDR1_(a))

#define _1GPLR(a, x)		((((x) & 0x7f) < 64) ? _2GPLR(a, x) : _GPLR2_(a))
#define _1GPDR(a, x)		((((x) & 0x7f) < 64) ? _2GPDR(a, x) : _GPDR2_(a))
#define _1GPSR(a, x)		((((x) & 0x7f) < 64) ? _2GPSR(a, x) : _GPSR2_(a))
#define _1GPCR(a, x)		((((x) & 0x7f) < 64) ? _2GPCR(a, x) : _GPCR2_(a))
#define _1GRER(a, x)		((((x) & 0x7f) < 64) ? _2GRER(a, x) : _GRER2_(a))
#define _1GFER(a, x)		((((x) & 0x7f) < 64) ? _2GFER(a, x) : _GFER2_(a))
#define _1GEDR(a, x)		((((x) & 0x7f) < 64) ? _2GEDR(a, x) : _GEDR2_(a))



#define GPLR(a, x) 			((((x) & 0x7f) < 96) ? _1GPLR(a, x) : _GPLR3_(a))
#define GPDR(a, x)			((((x) & 0x7f) < 96) ? _1GPDR(a, x) : _GPDR3_(a))
#define GPSR(a, x)			((((x) & 0x7f) < 96) ? _1GPSR(a, x) : _GPSR3_(a))
#define GPCR(a, x)			((((x) & 0x7f) < 96) ? _1GPCR(a, x) : _GPCR3_(a))
#define GRER(a, x)			((((x) & 0x7f) < 96) ? _1GRER(a, x) : _GRER3_(a))
#define GFER(a, x)			((((x) & 0x7f) < 96) ? _1GFER(a, x) : _GFER3_(a))
#define GEDR(a, x)			((((x) & 0x7f) < 96) ? _1GEDR(a, x) : _GEDR3_(a))

///==================================================================
#define _GAFR0_L_(y)		(&y->GAFR0_L)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define _GAFR0_U_(y)		(&y->GAFR0_U)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define _GAFR1_L_(x)		(&x->GAFR1_L)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define _GAFR1_U_(x)		(&x->GAFR1_U)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define _GAFR2_L_(x)		(&x->GAFR2_L)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define _GAFR2_U_(x)		(&x->GAFR2_U)  /* GPIO Alternate Function Select Register GPIO<95-80> */
#define _GAFR3_L_(x)		(&x->GAFR3_L)  /* GPIO Alternate Function Select Register GPIO<111:96> */
#define _GAFR3_U_(x)		(&x->GAFR3_U)  /* GPIO Alternate Function Select Register GPIO<127:112> */


#define _3GAFR(a, x)		((((x) & 0x10) > 0) ? _GAFR0_U_(a) : _GAFR0_L_(a))

#define _2GAFR(a, x)		((((x) & 0x7f) < 32) ? _3GAFR(a, x) : ((((x) & 0x10) > 0) ? _GAFR1_U_(a) : _GAFR1_L_(a)))

#define _1GAFR(a, x)		((((x) & 0x7f) < 64) ? _2GAFR(a, x) : ((((x) & 0x10) > 0) ? _GAFR2_U_(a) : _GAFR2_L_(a)))

#define GAFR(a, x)			((((x) & 0x7f) < 96) ? _1GAFR(a, x) : ((((x) & 0x10) > 0) ? _GAFR3_U_(a) : _GAFR3_L_(a)))

///==================================================================
#define PXA_IRQ(x)			(x)
#define GPIO_2_80_TO_IRQ(x)	PXA_IRQ((x) - 2 + 32)
#define IRQ_GPIO(x)			(((x)<2)?(IRQ_GPIO0+(x)):GPIO_2_80_TO_IRQ(x))


#define GFER_0(x)			(&x->GFER0)
#define GFER_1(x)			(&x->GFER1)
#define GFER_2(x)			(&x->GFER2)

#define GRER_0(x)			(&x->GRER0)
#define GRER_1(x)			(&x->GRER1)
#define GRER_2(x)			(&x->GRER2)


#define _GFER_x1(x, y)		((y<64)? GFER_1(x): GFER_2(x))
#define GFER_x(x, y)		((y < 32)? GFER_0(x): _GFER_x1(x, y))

#define _GRER_x1(x, y)		((y<64)? GRER_1(x): GRER_2(x))
#define GRER_x(x, y)		((y < 32)? GRER_0(x): _GRER_x1(x, y))

///==================================================================
typedef enum _sig_state{
	SIG_DOWN = 0,
	SIG_UP,
	SIG_FALLING,
	SIG_RISING
} SIGSTATE;

void set_GPIO_mode(volatile BULVERDE_GPIO_REG* gpioRegPt, int gpio_mode);

void set_GPIO_signal(volatile BULVERDE_GPIO_REG* gpioRegPt, int signum, SIGSTATE state);

void set_GPIO_IRQ_edge(volatile BULVERDE_GPIO_REG* gpioRegPt, int gpio_nr, SIGSTATE edge);




#if __cplusplus
}
#endif ///__cplusplus
#endif ///_PXA_GPIO_H