?? rt73.h
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typedef struct _RXD_STRUC { // Word 0 ULONG Owner:1; // 1: owned by ASIC, 0: owned by HOST driver ULONG Drop:1; // 1: drop without receiving to HOST ULONG U2M:1; // 1: this RX frame is unicast to me ULONG Mcast:1; // 1: this is a multicast frame ULONG Bcast:1; // 1: this is a broadcast frame ULONG MyBss:1; // 1: this frame belongs to the same BSSID ULONG Crc:1; // 1: CRC error ULONG Ofdm:1; // 1: this frame is received in OFDM rate// ULONG PhyErr:1; // 1: this frame is received with PHY error ULONG CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid ULONG KeyIndex:6; // decryption key actually used ULONG DataByteCnt:12; ULONG Rsv:1; ULONG CipherAlg:3; // word 1 ULONG PlcpSignal:8; // RX raw data rate reported by BBP ULONG PlcpRssi:8; // RSSI reported by BBP ULONG Rsv0:8; ULONG FrameOffset:7; ULONG Rsv1:1; // Word 2 ULONG Iv; // received IV if originally encrypted; for replay attack checking // Word 3 ULONG Eiv; // received EIV if originally encrypted; for replay attack checking // word 4 ULONG Rsv2; // The above 20-byte is called RXINFO and is prepared by MAC RX block and passed // the HOST driver. // The following fields are for DMA block and HOST usage only. Can't be touched // by ASIC MAC block. // Word 5 ULONG Rsv3; // BufPhyAddr;#if 0 // Word 6~15 ULONG Rsv3; ULONG Rsv4; ULONG Rsv5; ULONG Rsv6; ULONG Rsv7; ULONG Rsv8; ULONG Rsv9; ULONG Rsv10; ULONG Rsv11; ULONG Rsv12;#endif} RXD_STRUC, *PRXD_STRUC;#endif// =================================================================================// HOST-MCU communication data structure// =================================================================================//// H2M_MAILBOX_CSR: Host-to-MCU Mailbox//#ifdef BIG_ENDIANtypedef union _H2M_MAILBOX_STRUC { struct { ULONG Owner:8; ULONG CmdToken:8; // 0xff tells MCU not to report CmdDoneInt after excuting the command ULONG HighByte:8; ULONG LowByte:8; } field; ULONG word;} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;#elsetypedef union _H2M_MAILBOX_STRUC { struct { ULONG LowByte:8; ULONG HighByte:8; ULONG CmdToken:8; ULONG Owner:8; } field; ULONG word;} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;#endif//// M2H_CMD_DONE_CSR: MCU-to-Host command complete indication//#ifdef BIG_ENDIANtypedef union _M2H_CMD_DONE_STRUC { struct { ULONG CmdToken3; ULONG CmdToken2; ULONG CmdToken1; ULONG CmdToken0; } field; ULONG word;} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;#elsetypedef union _M2H_CMD_DONE_STRUC { struct { ULONG CmdToken0; ULONG CmdToken1; ULONG CmdToken2; ULONG CmdToken3; } field; ULONG word;} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;#endif//// MCU_INT_SOURCE_CSR, MCU_INT_MASK_CSR: MCU interrupt source/mask register//#ifdef BIG_ENDIANtypedef union _MCU_INT_SOURCE_STRUC { struct { ULONG :22; ULONG TBTTExpire:1; ULONG Twakeup:1; ULONG McuInt7:1; ULONG McuInt6:1; ULONG McuInt5:1; ULONG McuInt4:1; ULONG McuInt3:1; ULONG McuInt2:1; ULONG McuInt1:1; ULONG McuInt0:1; } field; ULONG word;} MCU_INT_SOURCE_STRUC, *PMCU_INT_SOURCE_STRUC, MCU_INT_MASK_STRUC, *PMCU_INT_MASK_STRUC;#elsetypedef union _MCU_INT_SOURCE_STRUC { struct { ULONG McuInt0:1; ULONG McuInt1:1; ULONG McuInt2:1; ULONG McuInt3:1; ULONG McuInt4:1; ULONG McuInt5:1; ULONG McuInt6:1; ULONG McuInt7:1; ULONG Twakeup:1; ULONG TBTTExpire:1; ULONG :22; } field; ULONG word;} MCU_INT_SOURCE_STRUC, *PMCU_INT_SOURCE_STRUC, MCU_INT_MASK_STRUC, *PMCU_INT_MASK_STRUC;#endif//// MCU_LEDCS: MCU LED Control Setting.//#ifdef BIG_ENDIANtypedef union _MCU_LEDCS_STRUC { struct { USHORT PolarityRDY_A:1; USHORT PolarityRDY_G:1; USHORT PolarityACT:1; USHORT PolarityGPIO_4:1; USHORT PolarityGPIO_3:1; USHORT PolarityGPIO_2:1; USHORT PolarityGPIO_1:1; USHORT PolarityGPIO_0:1; USHORT LinkAStatus:1; USHORT LinkGStatus:1; USHORT RadioStatus:1; USHORT LedMode:5; } field; USHORT word;} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;#elsetypedef union _MCU_LEDCS_STRUC { struct { USHORT LedMode:5; USHORT RadioStatus:1; USHORT LinkGStatus:1; USHORT LinkAStatus:1; USHORT PolarityGPIO_0:1; USHORT PolarityGPIO_1:1; USHORT PolarityGPIO_2:1; USHORT PolarityGPIO_3:1; USHORT PolarityGPIO_4:1; USHORT PolarityACT:1; USHORT PolarityRDY_G:1; USHORT PolarityRDY_A:1; } field; USHORT word;} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;#endif// =================================================================================// Register format// =================================================================================//// MAC_CSR1: System control register//#ifdef BIG_ENDIANtypedef union _MAC_CSR1_STRUC { struct { ULONG Rsvd1:29; ULONG HostReady:1; // Host is ready after initialization, 1: ready ULONG BbpReset:1; // Hardware reset BBP ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal } field; ULONG word;} MAC_CSR1_STRUC, *PMAC_CSR1_STRUC;#elsetypedef union _MAC_CSR1_STRUC { struct { ULONG SoftReset:1; // Software reset bit, 1: reset, 0: normal ULONG BbpReset:1; // Hardware reset BBP ULONG HostReady:1; // Host is ready after initialization, 1: ready ULONG Rsvd1:29; } field; ULONG word;} MAC_CSR1_STRUC, *PMAC_CSR1_STRUC;#endif//// MAC_CSR2: STA MAC register 0//#ifdef BIG_ENDIANtypedef union _MAC_CSR2_STRUC { struct { UCHAR Byte3; // MAC address byte 3 UCHAR Byte2; // MAC address byte 2 UCHAR Byte1; // MAC address byte 1 UCHAR Byte0; // MAC address byte 0 } field; ULONG word;} MAC_CSR2_STRUC, *PMAC_CSR2_STRUC;#elsetypedef union _MAC_CSR2_STRUC { struct { UCHAR Byte0; // MAC address byte 0 UCHAR Byte1; // MAC address byte 1 UCHAR Byte2; // MAC address byte 2 UCHAR Byte3; // MAC address byte 3 } field; ULONG word;} MAC_CSR2_STRUC, *PMAC_CSR2_STRUC;#endif//// MAC_CSR3: STA MAC register 1//#ifdef BIG_ENDIANtypedef union _MAC_CSR3_STRUC { struct { UCHAR Rsvd1; UCHAR U2MeMask; UCHAR Byte5; // MAC address byte 5 UCHAR Byte4; // MAC address byte 4 } field; ULONG word;} MAC_CSR3_STRUC, *PMAC_CSR3_STRUC;#elsetypedef union _MAC_CSR3_STRUC { struct { UCHAR Byte4; // MAC address byte 4 UCHAR Byte5; // MAC address byte 5 UCHAR U2MeMask; UCHAR Rsvd1; } field; ULONG word;} MAC_CSR3_STRUC, *PMAC_CSR3_STRUC;#endif//// MAC_CSR4: BSSID register 0//#ifdef BIG_ENDIANtypedef union _MAC_CSR4_STRUC { struct { UCHAR Byte3; // BSSID byte 3 UCHAR Byte2; // BSSID byte 2 UCHAR Byte1; // BSSID byte 1 UCHAR Byte0; // BSSID byte 0 } field; ULONG word;} MAC_CSR4_STRUC, *PMAC_CSR4_STRUC;#elsetypedef union _MAC_CSR4_STRUC { struct { UCHAR Byte0; // BSSID byte 0 UCHAR Byte1; // BSSID byte 1 UCHAR Byte2; // BSSID byte 2 UCHAR Byte3; // BSSID byte 3 } field; ULONG word;} MAC_CSR4_STRUC, *PMAC_CSR4_STRUC;#endif//// MAC_CSR5: BSSID register 1//#ifdef BIG_ENDIANtypedef union _MAC_CSR5_STRUC { struct { USHORT Rsvd:14; USHORT BssIdMask:2; // 11: one BSSID, 00: 4 BSSID, 10 or 01: 2 BSSID UCHAR Byte5; // BSSID byte 5 UCHAR Byte4; // BSSID byte 4 } field; ULONG word;} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;#elsetypedef union _MAC_CSR5_STRUC { struct { UCHAR Byte4; // BSSID byte 4 UCHAR Byte5; // BSSID byte 5 USHORT BssIdMask:2; // 11: one BSSID, 00: 4 BSSID, 10 or 01: 2 BSSID USHORT Rsvd:14; } field; ULONG word;} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;#endif//// MAC_CSR8: SIFS/EIFS register#ifdef BIG_ENDIANtypedef union _MAC_CSR8_STRUC { struct { USHORT Eifs; // in unit of 1-us UCHAR SifsAfterRxOfdm; // in unit of 1-us UCHAR Sifs; // in unit of 1-us } field; ULONG word;} MAC_CSR8_STRUC, *PMAC_CSR8_STRUC;#elsetypedef union _MAC_CSR8_STRUC { struct { UCHAR Sifs; // in unit of 1-us UCHAR SifsAfterRxOfdm; // in unit of 1-us USHORT Eifs; // in unit of 1-us } field; ULONG word;} MAC_CSR8_STRUC, *PMAC_CSR8_STRUC;#endif//// MAC_CSR9: Back-Off control register//#ifdef BIG_ENDIANtypedef union _MAC_CSR9_STRUC { struct { ULONG Rsvd:15; ULONG CWSelect:1; // 1: CWmin/Cwmax select from register, 0:select from TxD ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1). ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1). ULONG SlotTime:8; // Slot time, default is 20us for 802.11B } field; ULONG word;} MAC_CSR9_STRUC, *PMAC_CSR9_STRUC;#elsetypedef union _MAC_CSR9_STRUC { struct { ULONG SlotTime:8; // Slot time, default is 20us for 802.11B ULONG CWMin:4; // Bit for Cwmin. default Cwmin is 31 (2^5 - 1). ULONG CWMax:4; // Bit for Cwmax, default Cwmax is 1023 (2^10 - 1). ULONG CWSelect:1; // 1: CWmin/Cwmax select from register, 0:select from TxD ULONG Rsvd:15; } field; ULONG word;} MAC_CSR9_STRUC, *PMAC_CSR9_STRUC;#endif//// MAC_CSR11: Power saving transition time register//#ifdef BIG_ENDIANtypedef union _MAC_CSR11_STRUC { struct { ULONG :12; ULONG Sleep2AwakeLatency:4; // in unit of 1-TU ULONG bAutoWakeupEnable:1; ULONG NumOfTBTTBeforeWakeup:7; // Number of beacon before wakeup ULONG DelayAfterLastTBTTBeforeWakeup:8; // Delay after Tbcn expired in units of 1-TU } field; ULONG word;} MAC_CSR11_STRUC, *PMAC_CSR11_STRUC;#elsetypedef union _MAC_CSR11_STRUC { struct { ULONG DelayAfterLastTBTTBeforeWakeup:8; // Delay after Tbcn expired in units of 1-TU ULONG NumOfTBTTBeforeWakeup:7; // Number of beacon before wakeup ULONG bAutoWakeupEnable:1; ULONG Sleep2AwakeLatency:4; // in unit of 1-TU ULONG :12; } field; ULONG word;} MAC_CSR11_STRUC, *PMAC_CSR11_STRUC;#endif//// MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1)//#ifdef BIG_ENDIANtypedef union _MAC_CSR12_STRUC { struct { ULONG :28; ULONG BbpRfStatus:1; // 0: not ready, 1:ready ULONG ForceWakeup:1; // ForceWake has high privilege than PutToSleep when both set ULONG PutToSleep:1; ULONG CurrentPowerState:1; // 0:sleep, 1:awake } field; ULONG word;} MAC_CSR12_STRUC, *PMAC_CSR12_STRUC;#elsetypedef union _MAC_CSR12_STRUC { struct { ULONG CurrentPowerState:1; // 0:sleep, 1:awake ULONG PutToSleep:1; ULONG ForceWakeup:1; // ForceWake has high privilege than PutToSleep when both set ULONG BbpRfStatus:1; // 0: not ready, 1:ready ULONG :28; } field; ULONG word;} MAC_CSR12_STRUC, *PMAC_CSR12_STRUC;#endif//// MAC_CSR14: LED control register//#ifdef BIG_ENDIANtypedef union _MAC_CSR14_STRUC { struct { ULONG :12; ULONG SwLed2:1; ULONG HwLedPolarity:1; // 0: active low, 1: active high ULONG SwLed1:1; // s/w LED, 1: ON, 0: OFF ULONG HwLed:1; // h/w TX activity, 1: normal OFF, blinking upon TX, 0: normal ON, blinking upon TX ULONG OffPeriod:8; // Off period in unit of 1-ms, default 30ms ULONG OnPeriod:8; // On period in unit of 1-ms, default 70ms } field; ULONG word;} MAC_CSR14_STRUC, *PMAC_CSR14_STRUC;#elsetypedef union _MAC_CSR14_STRUC { struct { ULONG OnPeriod:8; // On period, default 70ms ULONG OffPeriod:8; // Off period, default 30ms ULONG HwLed:1; // h/w TX activity, 1: normal OFF, blinking upon TX, 0: normal ON, blinking upon TX ULONG SwLed1:1; // s/w LED, 1: ON, 0: OFF ULONG HwLedPolarity:1; // 0: active low, 1: active high ULONG SwLed2:1; ULONG :12; } field; ULONG word;} MAC_CSR14_STRUC, *PMAC_CSR14_STRUC;#endif//// TXRX_CSR0: TX/RX configuration register//#ifdef BIG_ENDIANtypedef union TXRX_CSR0_STRUC { struct { ULONG :5; ULONG TxWithoutWaitingSBox:1; ULONG DropAckCts:1; // 1: drop received ACK and CTS ULONG DropBcast:1; // Drop broadcast frames ULONG DropMcast:1; // Drop multicast frames ULONG DropVerErr:1; // Drop version error frame ULONG DropToDs:1; // Drop fram ToDs bit is true ULONG DropNotToMe:1; // Drop not to me unicast frame ULONG DropControl:1; // Drop control frame ULONG DropPhyErr:1; // Drop physical error ULONG DropCRCErr:1; // Drop CRC error ULONG DisableRx:1; // Disable Rx engine ULONG AutoTxSeq:1; // 1: ASIC auto replace sequence# in outgoing frame ULONG TsfOffset:6; // default is 24 ULONG RxAckTimeout:9; } field; ULONG word;} TXRX_CSR0_STRUC, *PTXRX_CSR0_STRUC;#elsetypedef union _TXRX_CSR0_STRUC {
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