?? em78p468.inc
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;******************************************************;
; ;
; Tilte: EM78x468x include file ;
; Description: The Definition of EM78x468x Registers ;
; Company: Elan Electronic Corp. ;
; Author: Brad Chen ;
; Date: 3/10/2005 ;
; Version: v1.0 ;
; Font: Fixedsys ;
; ;
;******************************************************;
;
;======================================================;
; Operational Registers Define ;
;======================================================;
;
;======================================================;
; Register R0~RF ;
;======================================================;
;
; Indirect Addressing register
;
R0 == 0x00
IAR == 0x00
;
; Time Clock/Counter
;
R1 == 0x01
TCC == 0x01 ; TCC Counter Preset
;
; Program Counter
;
R2 == 0X02
PC == 0X02
;
; Status Register and ROM Page Select Register
;
R3 == 0X03
SR == 0X03
;
;{
PS1 == 0x06 ; Page Select Bit[1]
PS0 == 0x05 ; Page Select Bit[0]
;
; |-----|-----|-----------------------------|
; | PS1 | PS0 | Program ROM Page and Address|
; |-----|-----|-----------------------------|
; | 0 | 0 | Page 0 (0x000~0x3FF) |
; | 0 | 1 | Page 1 (0x400~0x7FF) |
; | 1 | 0 | Page 2 (0x800~0xBFF) |
; | 1 | 1 | Page 3 (0xC00~0xFFF) |
; |-----|-----|-----------------------------|
;
T == 0x04 ; Time-Out Bit
P == 0x03 ; Power Down Bit
Z == 0x02 ; Zero Flag
DC == 0x01 ; Auxiliary Carry Flag
C == 0x00 ; Carry Flag
;
mPS1 == 0x40 ; Page Select Bit[1]
mPS0 == 0x20 ; Page Select Bit[0]
mT == 0x10 ; Time-Out Bit
mP == 0x08 ; Power Down Bit
mZ == 0x04 ; Zero Flag
mDC == 0x02 ; Auxiliary Carry Flag
mC == 0x01 ; Carry Flag
;
; Example
; choose Page 2
; method 1
; {
; MOV A,@(mPS1)
; MOV SR,A
; }
; method 2
; {
; BS SR,PS1
; BC SR,PS0
; }
;}
;
; RAM Select Register (RSR)
;
R4 == 0X04
RSR == 0X04
;{ ; Bits 7~6 are determoned the R20~R3F which bank is active
; Bits 5~0 are used to select registers(address: 00~3F)
; in the indirect addressing mode
;
RBS1 == 0x07 ; R20~R3F ram bank select bit
RBS0 == 0x06 ; it can using "bank" instruction to set these bits.
;
RSR5 == 0x05 ;
RSR4 == 0x04 ;
RSR3 == 0x03 ;
RSR2 == 0x02 ;
RSR1 == 0x01 ;
RSR0 == 0x00 ;
;
mRBS1 == 0x80 ; R20~R3F ram bank select bit
mRBS0 == 0x40 ; it can using "bank" instruction to set these bits.
;
mRSR5 == 0x20 ;
mRSR4 == 0x10 ;
mRSR3 == 0x08 ;
mRSR2 == 0x04 ;
mRSR1 == 0x02 ;
mRSR0 == 0x01 ;
;}
;
; Port 5 data and IOC Page Select Register
;
R5 == 0X05
PORT5 == 0X05
;
;{
R57 == 0x07 ; I/O data of P5.7
R56 == 0x06 ; I/O data of P5.6
R55 == 0x05 ; I/O data of P5.5
R54 == 0x04 ; I/O data of P5.4
; bits 3~1 not use
IOCPAGE == 0x00 ; IOC5~IOCF Page Select Bit.
; "0" : Page0 -> Select IOC50~IOCF0
; "1" : Page1 -> Select IOC61~IOCE1
;
mR57 == 0x80 ; I/O data of P5.7
mR56 == 0x40 ; I/O data of P5.6
mR55 == 0x20 ; I/O data of P5.5
mR54 == 0x10 ; I/O data of P5.4
; bits 3~1 not use
mIOCPAGE == 0x01 ; IOC5~IOCF Page Select Bit.
; "0" : Page0 -> Select IOC50~IOCF0
; "1" : Page1 -> Select IOC61~IOCE1
;}
;
; Port 6 data Register
;
R6 == 0X06
PORT6 == 0X06
;
;{
R67 == 0x07 ; I/O data of P6.7
R66 == 0x06 ; I/O data of P6.6
R65 == 0x05 ; I/O data of P6.5
R64 == 0x04 ; I/O data of P6.4
R63 == 0x03 ; I/O data of P6.3
R62 == 0x02 ; I/O data of P6.2
R61 == 0x01 ; I/O data of P6.1
R60 == 0x00 ; I/O data of P6.0
;
mR67 == 0x80 ; I/O data of P6.7
mR66 == 0x40 ; I/O data of P6.6
mR65 == 0x20 ; I/O data of P6.5
mR64 == 0x10 ; I/O data of P6.4
mR63 == 0x08 ; I/O data of P6.3
mR62 == 0x04 ; I/O data of P6.2
mR61 == 0x02 ; I/O data of P6.1
mR60 == 0x01 ; I/O data of P6.0
;}
;
; Port 7 data Register
;
R7 == 0X07
PORT7 == 0X07
;
;{
R77 == 0x07 ; I/O data of P7.7
R76 == 0x06 ; I/O data of P7.6
R75 == 0x05 ; I/O data of P7.5
R74 == 0x04 ; I/O data of P7.4
R73 == 0x03 ; I/O data of P7.3
R72 == 0x02 ; I/O data of P7.2
R71 == 0x01 ; I/O data of P7.1
R70 == 0x00 ; I/O data of P7.0
;
mR77 == 0x80 ; I/O data of P7.7
mR76 == 0x40 ; I/O data of P7.6
mR75 == 0x20 ; I/O data of P7.5
mR74 == 0x10 ; I/O data of P7.4
mR73 == 0x08 ; I/O data of P7.3
mR72 == 0x04 ; I/O data of P7.2
mR71 == 0x02 ; I/O data of P7.1
mR70 == 0x01 ; I/O data of P7.0
;}
;
; Port 8 data Register
;
R8 == 0X08
PORT8 == 0X08
;
;{
R87 == 0x07 ; I/O data of P8.7
R86 == 0x06 ; I/O data of P8.6
R85 == 0x05 ; I/O data of P8.5
R84 == 0x04 ; I/O data of P8.4
R83 == 0x03 ; I/O data of P8.3
R82 == 0x02 ; I/O data of P8.2
R81 == 0x01 ; I/O data of P8.1
R80 == 0x00 ; I/O data of P8.0
;
mR87 == 0x80 ; I/O data of P8.7
mR86 == 0x40 ; I/O data of P8.6
mR85 == 0x20 ; I/O data of P8.5
mR84 == 0x10 ; I/O data of P8.4
mR83 == 0x08 ; I/O data of P8.3
mR82 == 0x04 ; I/O data of P8.2
mR81 == 0x02 ; I/O data of P8.1
mR80 == 0x01 ; I/O data of P8.0
;}
;
; LCD Control Register
;
R9 == 0X09
LCDCR == 0X09
;
;{
LBS == 0x07 ; LCD Bias Select Bit."0":1/2 Bias,"1":1/3 Bias
DS1 == 0x06 ; LCD Duty Select Bit[1]
DS0 == 0x05 ; LCD Duty Select Bit[0]
;
; |-----|-----|----------|
; | DS1 | DS0 | LCD Duty |
; |-----|-----|----------|
; | 0 | 0 | 1/2 Duty |
; | 0 | 1 | 1/3 Duty |
; | 1 | X | 1/4 Duty |
; |-----|-----|----------|
; bit 5 not use
LCDEN == 0x04 ; LCD Enable Bit."0":Disable,"1":Enable
LCDTYPE == 0x02 ; LCD Drive Waveform Select Bit
; "0" : A Type Waveform,
; "1" : B Type Waveform
LCDF1 == 0x01 ; LCD Frame Frequency Control Bit[1]
LCDF0 == 0x00 ; LCD Frame Frequency Control Bit[0]
;
; |-----|-----|------------------------|----|
; | | | LCD Frame Frequency | |
; |LCDF1|LCDF0|------------------------|Unit|
; | | |1/2 Duty|1/3Duty|1/4Duty| |
; |-----|-----|--------|-------|-------|----|
; | 0 | 0 | 64.0 | 63.5 | 64.0 | Hz |
; | 0 | 1 | 58.5 | 58.0 | 58.5 | Hz |
; | 1 | 0 | 53.9 | 53.5 | 53.9 | Hz |
; | 1 | 1 | 70.6 | 70.0 | 70.6 | Hz |
; |-----|-----|--------|-------|-------|----|
;
mLBS == 0x80 ; LCD Bias Select Bit
mDS1 == 0x40 ; LCD Duty Select Bit[1]
mDS0 == 0x20 ; LCD Duty Select Bit[0]
mLCDEN == 0x10 ; LCD Enable Bit
; bit 5 not use
mLCDTYPE == 0x04 ; LCD Drive Waveform Select Bit
mLCDF1 == 0x02 ; LCD Frame Frequency Control Bit[1]
mLCDF0 == 0x01 ; LCD Frame Frequency Control Bit[0]
;}
;
; LCD RAM Address
;
RA == 0X0A
LCD_ADDR == 0X0A
;
; LCD Data Buffer
;
RB == 0X0B
LCD_DB == 0X0B
;
; Counter/Timer Enable Register
;
RC == 0X0C
CNTER == 0X0C
;
;{
; bit 7~4 not use
LPWTEN == 0x03 ; LPWT Enable Bit
; "0" : Disable
; "1" : Enable
HPWTEN == 0x02 ; HPWT Enable Bit
; "0" : Disable
; "1" : Enable
CNT2EN == 0x01 ; Counter 2 Enable Bit
; "0" : Disable
; "1" : Enable
CNT1EN == 0x00 ; Counter 1 Enable Bit
; "0" : Disable
; "1" : Enable
;
; bit 7~4 not use
mLPWTEN == 0x08 ; LPWT Enable Bit
mHPWTEN == 0x04 ; HPWT Enable Bit
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