# 
# ===============================================================================
#                               Allegro PCB Router                               
# Copyright 1990-2006 Cadence Design Systems, Inc.  All Rights Reserved.
# ===============================================================================
# 
# Software licensed for sale by Cadence Design Systems, Inc.
# Current time = Mon May 04 10:55:43 2009
# 
# Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
# Running on: pc-20090426gjon, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
# Licensing: The program will not obey any unlicensed rules
# No graphics will be displayed.
# Design Name F:/wenjian/第十一章/自動(dòng)布線\plane.dsn
# Batch File Name: pasde.do
# Did File Name: F:/wenjian/第十一章/自動(dòng)布線/specctra.did
# Current time = Mon May 04 10:55:43 2009
# PCB F:/wenjian/第十一章/自動(dòng)布線
# Master Unit set up as: MIL 1000
# PCB Limits xlo=-1192.5000 ylo=-590.0000 xhi=4142.5000 yhi=4470.0000
# Total 69 Images Consolidated.
# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# Wires Processed 0, Vias Processed 0
# Using colormap in design file.
# Layers Processed: Signal Layers 2
# Layers Processed: Power Layers 2
# Components Placed 85, Images Processed 100, Padstacks Processed 13
# Nets Processed 182, Net Terminals 772
# PCB Area=21340000.000  EIC=59  Area/EIC=361694.915  SMDs=65
# Total Pin Count: 839
# Signal Connections Created 431
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Cpu Time = 0:00:00  Elapsed Time = 0:00:00
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自動(dòng)布線\plane.dsn
# Nets 182 Connections 572 Unroutes 572
# Signal Layers 2 Power Layers 2
# Wire Junctions 0, at vias 0 Total Vias 0
# Percent Connected    0.00
# Manhattan Length 337942.0000 Horizontal 160801.1650 Vertical 177140.8350
# Routed Length   0.0000 Horizontal   0.0000 Vertical   0.0000
# Ratio Actual / Manhattan   0.0000
# Unconnected Length 337942.0000 Horizontal 150311.0000 Vertical 187631.0000
# Total Conflicts: 0 (Cross: 0, Clear: 0, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Cpu Time = 0:00:00  Elapsed Time = 0:00:00
# Loading Do File pasde.do ...
# Loading Do File F:/wenjian/第十一章/自動(dòng)布線\plane_rules.do ...
# Nets VD0 and VD3 have been defined as a balanced pair.
# Nets RD3 and RD0 have been defined as a balanced pair.
# Nets RA3 and RA0 have been defined as a balanced pair.
# Nets BD0 and BD3 have been defined as a balanced pair.
# Nets N16740 and N16748 have been defined as a balanced pair.
# Nets BA0 and BA3 have been defined as a balanced pair.
# Nets D10 and D13 have been defined as a balanced pair.
# Nets A20 and A23 have been defined as a balanced pair.
# Nets A10 and A13 have been defined as a balanced pair.
# <<WARNING:>> Could not form pair of nets RCS3 and RCS0.
# <<WARNING:>> Could not form pair of nets Q3 and Q0.
# Nets D0 and D3 have been defined as a balanced pair.
# Nets RA13 and RA10 have been defined as a balanced pair.
# Nets A0 and A3 have been defined as a balanced pair.
# Nets BD10 and BD13 have been defined as a balanced pair.
# Colormap Written to File _notify.std
# Enter command <# Loading Do File C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaaj03820.tmp ...
# All Components Unselected.
# All Nets Unselected.
set route_diagonal 0
grid wire 0.010000 (direction x) (offset 0.000000)
grid wire 0.010000 (direction y) (offset 0.000000)
grid via 0.010000 (direction x) (offset 0.000000)
grid via 0.010000 (direction y) (offset 0.000000)
protect all wires
# All Wires Protected.
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
# Wires on layer TOP were Unprotected.
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
# Wires on layer BOTTOM were Unprotected.
cost via -1
# System default cost will be used.
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
# All Selected Wires Unprotected.
route 25 1
# Current time = Mon May 04 10:55:58 2009
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自動(dòng)布線\plane.dsn
# Nets 182 Connections 572 Unroutes 572
# Signal Layers 2 Power Layers 2
# Wire Junctions 0, at vias 0 Total Vias 0
# Percent Connected    0.00
# Manhattan Length 338257.0000 Horizontal 160989.9200 Vertical 177267.0800
# Routed Length   0.0000 Horizontal   0.0000 Vertical   0.0000
# Ratio Actual / Manhattan   0.0000
# Unconnected Length 338257.0000 Horizontal 149956.0000 Vertical 188301.0000
# 0 bend points have been removed.
# 0 bend points have been removed.
# 0 bend points have been removed.
# Start Route Pass 1 of 25
# Routing 572 wires.
# 36 bend points have been removed.
# 35 bend points have been removed.
# Total Conflicts: 1024 (Cross: 999, Clear: 25, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 535 Successes 535 Failures 0 Vias 284
# Cpu Time = 0:00:04  Elapsed Time = 0:00:05
# End Pass 1 of 25
# Start Route Pass 2 of 25
# Routing 798 wires.
# Total Conflicts: 598 (Cross: 528, Clear: 70, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 655 Successes 634 Failures 21 Vias 410
# Cpu Time = 0:00:10  Elapsed Time = 0:00:11
# Conflict Reduction  0.4160
# End Pass 2 of 25
# Start Route Pass 3 of 25
# Routing 1109 wires.
# 56 bend points have been removed.
# 105 bend points have been removed.
# Total Conflicts: 290 (Cross: 245, Clear: 45, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 1
# Attempts 695 Successes 677 Failures 18 Vias 465
# Cpu Time = 0:00:12  Elapsed Time = 0:00:12
# Conflict Reduction  0.5151
# End Pass 3 of 25
# Start Route Pass 4 of 25
# Routing 959 wires.
# Total Conflicts: 126 (Cross: 82, Clear: 44, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 693 Successes 682 Failures 11 Vias 486
# Cpu Time = 0:00:11  Elapsed Time = 0:00:11
# Conflict Reduction  0.5655
# End Pass 4 of 25
# Start Route Pass 5 of 25
# Routing 1141 wires.
# 69 bend points have been removed.
# 144 bend points have been removed.
# Total Conflicts: 78 (Cross: 46, Clear: 32, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 692 Successes 677 Failures 15 Vias 533
# Cpu Time = 0:00:13  Elapsed Time = 0:00:13
# Conflict Reduction  0.3810
# End Pass 5 of 25
# 0 bend points have been removed.
# 0 bend points have been removed.
# Start Route Pass 6 of 25
# Routing 123 wires.
# 4 bend points have been removed.
# 46 bend points have been removed.
# Total Conflicts: 32 (Cross: 16, Clear: 16, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 93 Successes 90 Failures 3 Vias 575
# Cpu Time = 0:00:06  Elapsed Time = 0:00:06
# End Pass 6 of 25
# Start Route Pass 7 of 25
# Routing 31 wires.
# 2 bend points have been removed.
# 21 bend points have been removed.
# Total Conflicts: 32 (Cross: 18, Clear: 14, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 22 Successes 21 Failures 1 Vias 571
# Cpu Time = 0:00:03  Elapsed Time = 0:00:02
# End Pass 7 of 25
# Start Route Pass 8 of 25
# Routing 22 wires.
# Total Conflicts: 12 (Cross: 5, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 17 Successes 17 Failures 0 Vias 572
# Cpu Time = 0:00:02  Elapsed Time = 0:00:02
# End Pass 8 of 25
# Start Route Pass 9 of 25
# Routing 13 wires.
# 2 bend points have been removed.
# 12 bend points have been removed.
# Total Conflicts: 14 (Cross: 10, Clear: 4, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 9 Successes 9 Failures 0 Vias 577
# Cpu Time = 0:00:03  Elapsed Time = 0:00:03
# End Pass 9 of 25
# Start Route Pass 10 of 25
# Routing 13 wires.
# 63 bend points have been removed.
# 6 bend points have been removed.
# Total Conflicts: 15 (Cross: 3, Clear: 12, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 11 Successes 11 Failures 0 Vias 583
# Cpu Time = 0:00:02  Elapsed Time = 0:00:03
# End Pass 10 of 25
# Start Route Pass 11 of 25
# Routing 11 wires.
# 1 bend points have been removed.
# 1 bend points have been removed.
# Total Conflicts: 17 (Cross: 1, Clear: 16, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 6 Successes 6 Failures 0 Vias 595
# Cpu Time = 0:00:02  Elapsed Time = 0:00:03
# End Pass 11 of 25
# Start Route Pass 12 of 25
# Routing 14 wires.
# <<WARNING:>> Net RD0 redundant connection.
# <<WARNING:>> Net RD0 redundant connection.
# 1 bend points have been removed.
# 5 bend points have been removed.
# Total Conflicts: 30 (Cross: 3, Clear: 27, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 9 Successes 9 Failures 0 Vias 590
# Cpu Time = 0:00:03  Elapsed Time = 0:00:03
# End Pass 12 of 25
# Start Route Pass 13 of 25
# Routing 22 wires.
# Total Conflicts: 24 (Cross: 3, Clear: 21, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 0
# Attempts 4 Successes 3 Failures 1 Vias 588
# Cpu Time = 0:00:01  Elapsed Time = 0:00:02