library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity jsqztj is
port( clk  :in std_logic;
        en :IN std_logic;
      dataout: buffer std_logic_vector(5 downto 0));
end jsqztj;

architecture behave of jsqztj is
type state_type is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31);
signal state:state_type;
begin
 process(clk)
  begin
   if clk'event and clk='1' then
   if(en='1') then
   case state is
    when s0 =>
       state <= s1;
       dataout <= ('0','1','0','0','0','0');
    when s1 =>
       state <= s2;
       dataout <= ('0','1','0','0','1','1');
    when s2 =>
       state <= s3;
       dataout <= ('0','1','0','1','0','0');
    when s3 =>
       state <= s4;
       dataout <= ('0','1','0','1','1','1');
    when s4 =>
       state <= s5;
       dataout <= ('0','1','1','0','0','0');
    when s5 =>
       state <= s6;
       dataout <= ('0','1','1','0','1','1');
    when s6 =>
       state <= s7;
       dataout <= ('0','1','1','1','0','0');
    when s7 =>
       state <= s8;
       dataout <= ('0','1','1','1','1','1');
    when s8 =>
       state <= s9;
       dataout <= ('0','0','0','1','0','0');
    when s9 =>
       state <= s10;
       dataout <= ('0','0','0','1','1','1');
    when s10 =>
       state <= s11;
       dataout <= ('0','0','1','0','0','0');
    when s11 =>
       state <= s12;
       dataout <= ('0','0','1','0','1','1');
    when s12 =>
       state <= s13;
       dataout <= ('0','0','1','1','0','0');
    when s13 =>
       state <= s14;
       dataout <= ('0','0','1','1','1','1');
    when s14 =>
       state <= s15;
       dataout <= ('0','0','0','0','0','0');
    when s15 =>
       state <= s16;
       dataout <= ('0','0','0','0','1','1');
    when s16 =>
       state <= s17;
       dataout <= ('1','0','0','0','0','0');
    when s17 =>
       state <= s18;
       dataout <= ('1','0','0','0','1','1');
    when s18 =>
       state <= s19;
       dataout <= ('1','0','0','1','0','0');
    when s19 =>
       state <= s20;
       dataout <= ('1','0','0','1','1','1');
    when s20 =>
       state <= s21;
       dataout <= ('1','0','1','0','0','0');
    when s21 =>
       state <= s22;
       dataout <= ('1','0','1','0','1','1');
    when s22=>
       state <= s23;
       dataout <= ('1','0','1','1','0','0');
    when s23 =>
       state <= s24;
       dataout <= ('1','0','1','1','1','1');
   when s24 =>
       state <= s25;
       dataout <= ('1','1','0','0','0','0');
    when s25 =>
       state <= s26;
       dataout <= ('1','1','0','0','1','1');
    when s26 =>
       state <= s27;
       dataout <= ('1','1','0','1','0','0');
    when s27 =>
       state <= s28;
       dataout <= ('1','1','0','1','1','1');
    when s28=>
       state <= s29;
       dataout <= ('1','1','1','0','0','0');
    when s29 =>
       state <= s30;
       dataout <= ('1','1','1','0','1','1');
    when s30 =>
       state <= s31;
       dataout <= ('1','1','1','1','0','0');
    when s31 =>
       state <= s0;
       dataout <= ('1','1','1','1','1','1');
   
   end case;
   end if;
   end if;
  end process;
end behave;