?? the mathworks deutschland - filter design toolbox - implementing the filter chain of a digital down-converter in hdl demo.htm
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setfilter(h,hcicnorm,<SPAN class=string>'Fs'</SPAN>,Fs_in);
</PRE><A
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<P>The other thing to note is that zooming in the passband region we
see that the CIC has about -0.4 dB of attenuation (droop) at 80 KHz,
which is within the bandwidth of interest. A CIC filter is
essentially a cascade of boxcar filters and therefore has a
sinc-like response which causes the droop. This droop needs to be
compensated by the FIR filter in the next stage. </P><PRE class=code>axis([0 .1 -0.8 0]);
</PRE><A
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<H3>Compensation FIR Decimator<A name=11></A></H3>
<P>The second stage of our DDC filter chain needs to compensate for
the passband droop caused by the CIC and decimate by 2. Since the
CIC has a sinc-like response, we can compensate for the droop with a
lowpass filter that has an inverse-sinc response in the passband.
This filter will operate at 1/64th the input sample rate which is
69.333 MHz, therefore its rate is 1.0833MHz. Instead of designing a
lowpass filter with an inverse-sinc passband response from scratch,
we'll use a canned function which lets us design a decimator with a
CIC Compensation (inverse-sinc) response directly. </P><PRE class=code><SPAN class=comment>% Filter specifications</SPAN>
Fs = 1.0833e6; <SPAN class=comment>% Sampling frequency 69.333MHz/64</SPAN>
Apass = 0.01; <SPAN class=comment>% dB</SPAN>
Astop = 60; <SPAN class=comment>% dB</SPAN>
Aslope = 60; <SPAN class=comment>% 60 dB slope over half the Nyquist range</SPAN>
Fpass = 80e3; <SPAN class=comment>% Hz passband-edge frequency</SPAN>
Fstop = 293e3; <SPAN class=comment>% Hz stopband-edge frequency</SPAN>
<SPAN class=comment>% Design decimation filter. D and Nsecs have been defined above as the</SPAN>
<SPAN class=comment>% differential delay and number of sections, respectively.</SPAN>
d = fdesign.decimator(2,<SPAN class=string>'ciccomp'</SPAN>,D,Nsecs,Fpass,Fstop,Apass,Astop,Fs);
hcfir = design(d,<SPAN class=string>'equiripple'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'StopbandShape'</SPAN>, <SPAN class=string>'linear'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'StopbandDecay'</SPAN>, Aslope);
<SPAN class=comment>% Now we have to define the fixed-point attributes of our multirate filter.</SPAN>
<SPAN class=comment>% By default, the fixed-point attributes of the accumulator and multipliers</SPAN>
<SPAN class=comment>% are set to ensure that full precision arithmetic is used, i.e. no</SPAN>
<SPAN class=comment>% quantization takes place.</SPAN>
set(hcfir,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'Arithmetic'</SPAN>, <SPAN class=string>'fixed'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'CoeffWordLength'</SPAN>, 16,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'InputWordLength'</SPAN>, 20,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'InputFracLength'</SPAN>, -12);
</PRE>
<P>Using the info command we can get a comprehensive report of the
FIR compensation filter, including the word lengths of the
accumulator and product, which are automatically determined. </P><PRE class=code>info(hcfir)
</PRE><PRE class=ans>Discrete-Time FIR Multirate Filter (real)
-----------------------------------------
Filter Structure : Direct-Form FIR Polyphase Decimator
Decimation Factor : 2
Polyphase Length : 11
Filter Length : 21
Stable : Yes
Linear Phase : Yes (Type 1)
Arithmetic : fixed
Numerator : s16,16 -> [-5.000000e-001 5.000000e-001)
Input : s20,-12 -> [-2.147484e+009 2.147484e+009)
Filter Internals : Full Precision
Output : s37,4 -> [-4.294967e+009 4.294967e+009) (auto deter
mined)
Product : s35,4 -> [-1073741824 1073741824) (auto determined)
Accumulator : s37,4 -> [-4.294967e+009 4.294967e+009) (auto deter
mined)
Round Mode : No rounding
Overflow Mode : No overflow
</PRE>
<P>Cascading the CIC with the inverse sinc filter we can see if we
eliminated the passband droop caused by the CIC.</P><PRE class=code>hcas1 = cascade(hcicnorm,hcfir);
set(h,<SPAN class=string>'Filters'</SPAN>, [hcicnorm,hcfir,hcas1],<SPAN class=string>'Fs'</SPAN>,[Fs_in,Fs_in/64,Fs_in]);
axis([0 .1 -0.8 0.8]);
legend(h,<SPAN class=string>'hcic'</SPAN>,<SPAN class=string>'hcfir'</SPAN>,<SPAN class=string>'cascade'</SPAN>);
</PRE><A
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onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_04.png',600,419, 'scrollbars=no,resizable=yes,status=no'); return false;"
onmouseout="window.status='';"
href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_04.png"><IMG
height=244 hspace=5
src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcfilterchaindemo_04_thumbnail.png"
width=350 vspace=5></A>
<P>As we can see in the filter response of the cascade of the two
filters, which is between the CIC response and the compensating FIR
response, the passband droop has been eliminated. </P>
<H3>Third Stage FIR Decimator<A name=15></A></H3>
<P>As indicated earlier the GSM spectral mask requires an
attenuation of 18 dB at 100 KHz. So, for our third and final stage
we can try a simple equiripple lowpass filter. Once again we need to
quantize the coefficients to 16 bits. This filter also needs to
decimate by 2. </P><PRE class=code>N = 62; <SPAN class=comment>% 63 taps</SPAN>
Fs = 541666; <SPAN class=comment>% 541.666 kHz</SPAN>
Fpass = 80e3;
Fstop = 100e3;
d = fdesign.decimator(2,<SPAN class=string>'lowpass'</SPAN>,<SPAN class=string>'N,Fp,Fst'</SPAN>,N,Fpass,Fstop,Fs);
hpfir = design(d,<SPAN class=string>'equiripple'</SPAN>,<SPAN class=string>'Wpass'</SPAN>,2); <SPAN class=comment>% Give more weight to passband</SPAN>
set(hpfir,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'Arithmetic'</SPAN>, <SPAN class=string>'fixed'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'CoeffWordLength'</SPAN>, 16,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'InputWordLength'</SPAN>, 20,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'InputFracLength'</SPAN>, -12);
</PRE>
<P>When defining a multirate filter by default the accumulator word
size is determined automatically to maintain full precision.
However, because we only have 20 bits for the output let's set the
output format to a word length of 20 bits and a fractional length of
-12. First, we must change the FilterInternals property's default
value from 'FullPrecision' to 'SpecifyPrecision'. </P><PRE class=code>set(hpfir,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'FilterInternals'</SPAN>, <SPAN class=string>'specifyPrecision'</SPAN>,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'outputWordLength'</SPAN>, 20,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'outputFracLength'</SPAN>,-12,<SPAN class=keyword>...</SPAN>
<SPAN class=string>'RoundMode'</SPAN>, <SPAN class=string>'round'</SPAN>,<SPAN class=keyword>...</SPAN><SPAN class=comment> % = nearest in SL</SPAN>
</PRE><PRE class=code> <SPAN class=string>'OverflowMode'</SPAN>, <SPAN class=string>'Saturate'</SPAN>);
</PRE>
<P>We can use the info method to view the filter details.</P><PRE class=code>info(hpfir)
</PRE><PRE class=ans>Discrete-Time FIR Multirate Filter (real)
-----------------------------------------
Filter Structure : Direct-Form FIR Polyphase Decimator
Decimation Factor : 2
Polyphase Length : 32
Filter Length : 63
Stable : Yes
Linear Phase : Yes (Type 1)
Arithmetic : fixed
Numerator : s16,16 -> [-5.000000e-001 5.000000e-001)
Input : s20,-12 -> [-2.147484e+009 2.147484e+009)
Filter Internals : Specify Precision
Output : s20,-12 -> [-2.147484e+009 2.147484e+009)
Product : s35,4 -> [-1073741824 1073741824)
Accumulator : s37,4 -> [-4.294967e+009 4.294967e+009)
Round Mode : round
Overflow Mode : saturate
</PRE>
<H3>Multistage Multirate DDC Filter Chain<A name=19></A></H3>
<P>Now that we have designed and quantized the three filters, we can
get the overall filter response by cascading the normalized CIC and
the two FIR filters. Again, we're using the normalized CIC filter to
ensure that the cascaded filter response is normalized to 0 dB. </P><PRE class=code>hcasnorm = cascade(hcicnorm,hcfir,hpfir);
set(h,<SPAN class=string>'Filters'</SPAN>,hcasnorm,<SPAN class=string>'Fs'</SPAN>,Fs_in,<SPAN class=string>'NumberofPoints'</SPAN>,8192*3);
axis([0 1 -200 10]); <SPAN class=comment>% Zoom-in</SPAN>
</PRE><A
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href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_05.png"><IMG
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<P>To see if the overall filter response meets the GSM
specifications, we can overlay the GSM spectral mask on the filter
response.</P><PRE class=code>drawgsmmask;
</PRE><A
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src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcfilterchaindemo_06_thumbnail.png"
width=350 vspace=5></A>
<P>We can see that our overall filter response is within the
constraints of the GSM spectral mask. We also need to ensure that
the passband ripple meets the requirement that it is less than 0.1
dB peak-to-peak. We can verify this by zooming in using the axis
command. </P><PRE class=code>axis([0 .09 -0.08 0.08]);
</PRE><A
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onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_07.png',600,419, 'scrollbars=no,resizable=yes,status=no'); return false;"
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href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcfilterchaindemo_07.png"><IMG
height=244 hspace=5
src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcfilterchaindemo_07_thumbnail.png"
width=350 vspace=5></A>
<P>Indeed the passband ripple is well below the 0.1 dB peak-to-peak
GSM requirement.</P>
<H3>Generate VHDL Code<A name=23></A></H3>
<P>FDATool also supports the generation of HDL code from the dialog
shown below.</P>
<P><A
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onclick="openWindow('/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemohdldialog.png',546,470, 'scrollbars=no,resizable=yes,status=no'); return false;"
onmouseout="window.status='';"
href="http://www.mathworks.de/products/demos/fullsize.html?src=/products/demos/shipping/filterdesign/ddcdemohdldialog.png"><IMG
height=301 hspace=5
src="The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.files/ddcdemohdldialog_thumbnail.png"
width=350 vspace=5></A> </P>
<P>From FDATool as well as the command line you can generate VHDL or
Verilog code as well as test benches in VHDL, Verilog, or as
ModelSim? .do files. Also, you have the ability to customize your
generated HDL code by specifying many options to meet your coding
standards and guidelines. </P>
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