/* ixp425Pci_p.h - private header file for the ixp425 PCI unit driver *//* Copyright 2002 Wind River Systems, Inc. *//*modification history--------------------01b,27feb03,jb3  add C++ protection01a,05jun02,jb  initial version...*/#ifndef IXP425PCI_P_H#define IXP425PCI_P_H#ifdef __cplusplusextern "C" {#endif#include "dllLib.h"#include "ixp425Pci.h"#ifndef BIT#define BIT(x) (1<<(x))#endif/* Mask definitions*/#define IXP425_PCI_TOP_WORD_OF_LONG_MASK        0xffff0000#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK        0xff000000#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK     0x0000ffff#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK   0x0000000f#define IXP425_PCI_MAX_UINT32                   0xffffffff#define IXP425_PCI_BAR_QUERY                    0xffffffff/* PCI command bits */#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable *//* PCI base address mask bits */#define PCI_PCIADDR_MASK 0x00ffffff#define PCI_MEMBASE_MASK	~0xf	/* mask for memory base address */#define PCI_IOBASE_MASK		~0x3	/* mask for IO base address */#define PCI_BASE_IO		0x1	/* IO space indicator */#define PCI_BASE_BELOW_1M	0x2	/* memory locate below 1MB */#define PCI_BASE_IN_64BITS	0x4	/* memory locate anywhere in 64 bits */#define PCI_BASE_PREFETCH	0x8	/* memory prefetchable *//* PCI header type bits */#define PCI_HEADER_TYPE_MASK	0x7f	/* mask for header type */#define PCI_HEADER_PCI_PCI	0x01	/* PCI to PCI bridge */#define PCI_HEADER_MULTI_FUNC	0x80	/* multi function device *//*PCI configuration regs.*/#define	PCI_CFG_VENDOR_ID	0x00#define	PCI_CFG_DEVICE_ID	0x02#define	PCI_CFG_COMMAND		0x04#define	PCI_CFG_STATUS		0x06#define	PCI_CFG_REVISION	0x08#define	PCI_CFG_PROGRAMMING_IF	0x09#define	PCI_CFG_SUBCLASS	0x0a#define	PCI_CFG_CLASS		0x0b#define	PCI_CFG_CACHE_LINE_SIZE	0x0c#define	PCI_CFG_LATENCY_TIMER	0x0d#define	PCI_CFG_HEADER_TYPE	0x0e#define	PCI_CFG_BIST		0x0f#define	PCI_CFG_BASE_ADDRESS_0	0x10#define	PCI_CFG_BASE_ADDRESS_1	0x14#define	PCI_CFG_BASE_ADDRESS_2	0x18#define	PCI_CFG_BASE_ADDRESS_3	0x1c#define	PCI_CFG_BASE_ADDRESS_4	0x20#define	PCI_CFG_BASE_ADDRESS_5	0x24#define	PCI_CFG_CIS		0x28#define	PCI_CFG_SUB_VENDOR_ID	0x2c#define	PCI_CFG_SUB_SYSTEM_ID	0x2e#define	PCI_CFG_EXPANSION_ROM	0x30#define	PCI_CFG_RESERVED_0	0x34#define	PCI_CFG_RESERVED_1	0x38#define	PCI_CFG_DEV_INT_LINE	0x3c#define	PCI_CFG_DEV_INT_PIN	0x3d#define	PCI_CFG_MIN_GRANT	0x3e#define	PCI_CFG_MAX_LATENCY	0x3f#define PCI_CFG_SPECIAL_USE     0x41#define PCI_CFG_MODE            0x43/*Configuration command bit definitions*/#define PCI_CFG_CMD_IOAE BIT(0) #define PCI_CFG_CMD_MAE  BIT(1)#define PCI_CFG_CMD_BME  BIT(2)#define PCI_CFG_CMD_MWIE BIT(4)#define PCI_CFG_CMD_SER  BIT(8)#define PCI_CFG_CMD_FBBE BIT(9)#define PCI_CFG_CMD_MDPE BIT(24)#define PCI_CFG_CMD_STA  BIT(27)#define PCI_CFG_CMD_RTA  BIT(28)#define PCI_CFG_CMD_RMA  BIT(29)#define PCI_CFG_CMD_SSE  BIT(30)#define PCI_CFG_CMD_DPE  BIT(31)/* PCI-to-PCI bridge configuration register offsets *//* Note that only modulo-4 addresses are written to the address register */#define	PCI_CFG_PRIMARY_BUS	0x18#define	PCI_CFG_SECONDARY_BUS	0x19#define	PCI_CFG_SUBORDINATE_BUS	0x1a#define	PCI_CFG_SEC_LATENCY	0x1b#define	PCI_CFG_IO_BASE		0x1c#define	PCI_CFG_IO_LIMIT	0x1d#define	PCI_CFG_SEC_STATUS	0x1e#define	PCI_CFG_MEM_BASE	0x20#define	PCI_CFG_MEM_LIMIT	0x22#define	PCI_CFG_PRE_MEM_BASE	0x24#define	PCI_CFG_PRE_MEM_LIMIT	0x26#define	PCI_CFG_PRE_MEM_BASE_U	0x28#define	PCI_CFG_PRE_MEM_LIMIT_U	0x2c#define	PCI_CFG_IO_BASE_U	0x30#define	PCI_CFG_IO_LIMIT_U	0x32#define	PCI_CFG_ROM_BASE	0x38#define	PCI_CFG_BRG_INT_LINE	0x3c#define	PCI_CFG_BRG_INT_PIN	0x3d#define	PCI_CFG_BRIDGE_CONTROL	0x3e/*Register addressing definitions for PCI controller configuration  and status registers*/#define PCI_CSR_BASE (0xC0000000)#define PCI_NP_AD_OFFSET       (0x00)#define PCI_NP_CBE_OFFSET      (0x04)#define PCI_NP_WDATA_OFFSET    (0x08)#define PCI_NP_RDATA_OFFSET    (0x0C)#define PCI_CRP_OFFSET         (0x10)#define PCI_CRP_WDATA_OFFSET   (0x14)#define PCI_CRP_RDATA_OFFSET   (0x18)#define PCI_CSR_OFFSET         (0x1C)#define PCI_ISR_OFFSET         (0x20)#define PCI_INTEN_OFFSET       (0x24)#define PCI_DMACTRL_OFFSET     (0x28)#define PCI_AHBMEMBASE_OFFSET  (0x2C)#define PCI_AHBIOBASE_OFFSET   (0x30)#define PCI_PCIMEMBASE_OFFSET  (0x34)#define PCI_AHBDOORBELL_OFFSET (0x38)#define PCI_PCIDOORBELL_OFFSET (0x3C)#define PCI_ATPDMA0_AHBADDR    (0x40)#define PCI_ATPDMA0_PCIADDR    (0x44)#define PCI_ATPDMA0_LENADDR    (0x48)#define PCI_ATPDMA1_AHBADDR    (0x4C)#define PCI_ATPDMA1_PCIADDR    (0x50)#define PCI_ATPDMA1_LENADDR    (0x54)#define PCI_PTADMA0_AHBADDR    (0x58)#define PCI_PTADMA0_PCIADDR    (0x5C)#define PCI_PTADMA0_LENADDR    (0x60)#define PCI_PTADMA1_AHBADDR    (0x64)#define PCI_PTADMA1_PCIADDR    (0x68)#define PCI_PTADMA1_LENADDR    (0x6C)/*Non prefetch registers bit definitions*/#define NP_CMD_INTACK      (0x0)#define NP_CMD_SPECIAL     (0x1)#define NP_CMD_IOREAD      (0x2)#define NP_CMD_IOWRITE     (0x3)#define NP_CMD_MEMREAD     (0x6)#define NP_CMD_MEMWRITE    (0x7)#define NP_CMD_CONFIGREAD  (0xa)#define NP_CMD_CONFIGWRITE (0xb)#define PCI_NP_CBE_BESL  (4)#define PCI_NP_AD_FUNCSL (8)/*Configuration Port register bit definitions*/#define PCI_CRP_WRITE BIT(16)/*CSR Register bit definitions*/#define PCI_CSR_HOST  BIT(0)#define PCI_CSR_ARBEN BIT(1)#define PCI_CSR_ADS   BIT(2)#define PCI_CSR_PDS   BIT(3)#define PCI_CSR_ABE   BIT(4)#define PCI_CSR_DBT   BIT(5)#define PCI_CSR_ASE   BIT(8)#define PCI_CSR_IC    BIT(15)/*ISR (Interrupt status) Register bit definitions*/#define PCI_ISR_PSE   BIT(0)#define PCI_ISR_PFE   BIT(1)#define PCI_ISR_PPE   BIT(2)#define PCI_ISR_AHBE  BIT(3)#define PCI_ISR_APDC  BIT(4)#define PCI_ISR_PADC  BIT(5)#define PCI_ISR_ADB   BIT(6)#define PCI_ISR_PDB   BIT(7)/*INTEN (Interrupt Enable) Register bit definitions*/#define PCI_INTEN_PSE   BIT(0)#define PCI_INTEN_PFE   BIT(1)#define PCI_INTEN_PPE   BIT(2)#define PCI_INTEN_AHBE  BIT(3)#define PCI_INTEN_APDC  BIT(4)#define PCI_INTEN_PADC  BIT(5)#define PCI_INTEN_ADB   BIT(6)#define PCI_INTEN_PDB   BIT(7)/*DMACTRL DMA Control and status Register*/#define PCI_DMACTRL_APDCEN  BIT(0)#define PCI_DMACTRL_APDC0   BIT(4)#define PCI_DMACTRL_APDE0   BIT(5)#define PCI_DMACTRL_APDC1   BIT(6)#define PCI_DMACTRL_APDE1   BIT(7)#define PCI_DMACTRL_PADCEN  BIT(8)#define PCI_DMACTRL_PADC0   BIT(12)#define PCI_DMACTRL_PADE0   BIT(13)#define PCI_DMACTRL_PADC1   BIT(14)#define PCI_DMACTRL_PADE1   BIT(15)/*DMA length registers bit definitions - these are common to all four DMA length registers*/#define PCI_DMA_LEN_BE BIT(28)#define PCI_DMA_LEN_EN BIT(31)#define IXP425_PCI_DMA_MAX_LEN 0xffff/* number of IRQs mapped on PCI interrupt */#define PCI_IRQ_LINES		4/*Size of DMA request pools*/#define NUM_REQ_POOL 10/*Register access macros*/#ifndef IX_PCI_UNIT_TEST#define REG_WRITE(b,o,v) (*(volatile UINT32*)((b+o))=(v))#define REG_READ(b,o,v)  ((v)=(*(volatile UINT32*)((b+o))))#else#define REG_WRITE(b,o,v) registerWriteStub(b,o,v)#define REG_READ(b,o,v)  registerReadStub(b,o,&v)#endif/* structure for the device & bridge header */typedef struct pciHeaderDevice    {    UINT16	vendorId;	/* vendor ID */    UINT16	deviceId;	/* device ID */    UINT16	command;	/* command register */    UINT16	status;		/* status register */    UINT8	revisionId;	/* revision ID */    UINT8	classCode;	/* class code */    UINT8	subClass;	/* sub class code */    UINT8	progIf;		/* programming interface */    UINT8	cacheLine;	/* cache line */    UINT8	latency;	/* latency time */    UINT8	headerType;	/* header type */    UINT8	bist;		/* BIST */    UINT32      base0;		/* base address 0 */    UINT32      base1;		/* base address 1 */    UINT32      base2;		/* base address 2 */    UINT32      base3;		/* base address 3 */    UINT32      base4;		/* base address 4 */    UINT32      base5;		/* base address 5 */    UINT32      cis;		/* cardBus CIS pointer */    UINT16      subVendorId;	/* sub system vendor ID */    UINT16      subSystemId;	/* sub system ID */    UINT32      romBase;	/* expansion ROM base address */    UINT32      reserved0;	/* reserved */    UINT32      reserved1;	/* reserved */    UINT8       intLine;	/* interrupt line */    UINT8       intPin;		/* interrupt pin */    UINT8       minGrant;	/* min Grant */    UINT8       maxLatency;	/* max Latency */    } PCI_HEADER_DEVICE;typedef struct pciHeaderBridge    {    UINT16	vendorId;	/* vendor ID */    UINT16	deviceId;	/* device ID */    UINT16	command;	/* command register */    UINT16	status;		/* status register */    UINT8	revisionId;	/* revision ID */    UINT8	classCode;	/* class code */    UINT8	subClass;	/* sub class code */    UINT8	progIf;		/* programming interface */    UINT8	cacheLine;	/* cache line */    UINT8	latency;	/* latency time */    UINT8	headerType;	/* header type */    UINT8	bist;		/* BIST */    UINT32	base0;		/* base address 0 */    UINT32	base1;		/* base address 1 */    UINT8	priBus;		/* primary bus number */    UINT8	secBus;		/* secondary bus number */    UINT8	subBus;		/* subordinate bus number */    UINT8	secLatency;	/* secondary latency timer */    UINT8	ioBase;		/* IO base */    UINT8	ioLimit;	/* IO limit */    UINT16	secStatus;	/* secondary status */    UINT16	memBase;	/* memory base */    UINT16	memLimit;	/* memory limit */    UINT16	preBase;	/* prefetchable memory base */    UINT16	preLimit;	/* prefetchable memory limit */    UINT32      preBaseUpper;	/* prefetchable memory base upper 32 bits */    UINT32	preLimitUpper;	/* prefetchable memory base upper 32 bits */    UINT16	ioBaseUpper;	/* IO base upper 16 bits */    UINT16	ioLimitUpper;	/* IO limit upper 16 bits */    UINT32	reserved;	/* reserved */    UINT32	romBase;	/* expansion ROM base address */    UINT8	intLine;	/* interrupt line */    UINT8	intPin;		/* interrupt pin */    UINT16	control;	/* bridge control */    } PCI_HEADER_BRIDGE;typedef struct pciIntRtn    {    DL_NODE	node;		/* double link list */    VOIDFUNCPTR	routine;	/* interrupt handler */    UINT32	parameter;	/* parameter of the handler */    } PCI_INT_RTN;typedef struct pciCallbackIntRtn    {    DL_NODE	node;		/* double link list */    PCICALLBACKFUNC routine;	/* interrupt handler */    } PCI_CALLBACK_INT_RTN;#ifdef __cplusplus}#endif#endif /* IXP425PCI_P_H */