+----------------------------------+-----------------+-----------------+-----------------------------------------------------+
; compare.vhd                      ; yes             ; User VHDL File  ; C:/Documents and Settings/user/桌面/suo/compare.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 10    ;
;     -- Combinational with no register       ; 9     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 1     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 7     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 10    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 1     ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; ok    ;
; Maximum fan-out                             ; 6     ;
; Total fan-out                               ; 41    ;
; Average fan-out                             ; 1.32  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |compare                   ; 10 (10)     ; 1            ; 0           ; 0    ; 21   ; 0            ; 9 (9)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |compare            ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; f0[0]                                              ; ok                  ; yes                    ;
; f0[1]                                              ; ok                  ; yes                    ;
; f0[2]                                              ; ok                  ; yes                    ;
; f0[3]                                              ; ok                  ; yes                    ;
; f0[4]                                              ; ok                  ; yes                    ;
; f0[5]                                              ; ok                  ; yes                    ;
; Number of user-specified and inferred latches = 6  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Source assignments for Top-level Entity: |compare ;
+----------------+-------+------+-------------------+
; Assignment     ; Value ; From ; To                ;
+----------------+-------+------+-------------------+
; POWER_UP_LEVEL ; Low   ; -    ; g0                ;
+----------------+-------+------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Dec 16 20:02:37 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off compare -c compare
Info: Found 2 design units, including 1 entities, in source file compare.vhd
    Info: Found design unit 1: compare-behave
    Info: Found entity 1: compare
Info: Elaborating entity "compare" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at compare.vhd(26): signal "ok" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at compare.vhd(15): inferring latch(es) for signal or variable "f0", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[0]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[1]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[2]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[3]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[4]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[5]"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 7 output pins
    Info: Implemented 10 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Dec 16 20:02:39 2008
    Info: Elapsed time: 00:00:02