library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare is
port(ok,clk : in std_logic;--計時時鐘
    d,e : in std_logic_vector(5 downto 0);--開鎖時輸入的密碼
     f: out std_logic_vector(5 downto 0);--鎖的原始密碼
     g: out std_logic);   --密碼正確與否的輸出
end;
architecture behave of compare is
signal f0 : std_logic_vector (5 downto 0);
signal g0 : std_logic :='0';
--signal ok: std_logic := '0';
begin
process( d,e,clk)
begin
if clk'event and clk = '1' then
if d(5 downto 0)= e (5 downto 0) then
--f0(5 downto 0) <= d (5 downto 0);
g0 <= '1';
else
g0 <= '0';
--ok0 <= '1';
end if;
end if;
if ok = '1' then f0(5 downto 0) <= d (5 downto 0);
end if;
end process;
f(5 downto 0) <= f0 (5 downto 0);
g <= g0;
end behave;