# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: Calculator_Design.tcl
# Generated on: Fri Nov 02 11:08:02 2012

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "Calculator_Design"]} {
		puts "Project Calculator_Design is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists Calculator_Design]} {
		project_open -revision Calculator_Design Calculator_Design
	} else {
		project_new -revision Calculator_Design Calculator_Design
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name FAMILY "Cyclone II"
	set_global_assignment -name DEVICE EP2C35F672C6
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP1"
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:02:45  NOVEMBER 02, 2012"
	set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
	set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
	set_global_assignment -name VERILOG_FILE ../src/key_scan.v
	set_global_assignment -name VERILOG_FILE ../src/mult_4bits.v
	set_global_assignment -name VERILOG_FILE ../src/seg7_lut.v
	set_global_assignment -name VERILOG_FILE ../src/adder_4bits.v
	set_global_assignment -name VERILOG_FILE ../src/Calculator_Design.v
	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
	set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
	set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
	set_global_assignment -name MISC_FILE "D:/Altera_Project/LabTest/Calculator_Design/dev/Calculator_Design.dpf"
	set_global_assignment -name USE_CONFIGURATION_DEVICE ON
	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
	set_location_assignment PIN_N25 -to key_switch[0]
	set_location_assignment PIN_N26 -to key_switch[1]
	set_location_assignment PIN_P25 -to key_switch[2]
	set_location_assignment PIN_AE14 -to key_switch[3]
	set_location_assignment PIN_AF14 -to key_switch[4]
	set_location_assignment PIN_AD13 -to key_switch[5]
	set_location_assignment PIN_AC13 -to key_switch[6]
	set_location_assignment PIN_C13 -to key_switch[7]
	set_location_assignment PIN_AF10 -to oSEG0[0]
	set_location_assignment PIN_AB12 -to oSEG0[1]
	set_location_assignment PIN_AC12 -to oSEG0[2]
	set_location_assignment PIN_AD11 -to oSEG0[3]
	set_location_assignment PIN_AE11 -to oSEG0[4]
	set_location_assignment PIN_V14 -to oSEG0[5]
	set_location_assignment PIN_V13 -to oSEG0[6]
	set_location_assignment PIN_V20 -to oSEG1[0]
	set_location_assignment PIN_V21 -to oSEG1[1]
	set_location_assignment PIN_W21 -to oSEG1[2]
	set_location_assignment PIN_Y22 -to oSEG1[3]
	set_location_assignment PIN_AA24 -to oSEG1[4]
	set_location_assignment PIN_AA23 -to oSEG1[5]
	set_location_assignment PIN_AB24 -to oSEG1[6]
	set_location_assignment PIN_AB23 -to oSEG2[0]
	set_location_assignment PIN_V22 -to oSEG2[1]
	set_location_assignment PIN_AC25 -to oSEG2[2]
	set_location_assignment PIN_AC26 -to oSEG2[3]
	set_location_assignment PIN_AB26 -to oSEG2[4]
	set_location_assignment PIN_AB25 -to oSEG2[5]
	set_location_assignment PIN_Y24 -to oSEG2[6]
	set_location_assignment PIN_Y23 -to oSEG3[0]
	set_location_assignment PIN_AA25 -to oSEG3[1]
	set_location_assignment PIN_AA26 -to oSEG3[2]
	set_location_assignment PIN_Y26 -to oSEG3[3]
	set_location_assignment PIN_Y25 -to oSEG3[4]
	set_location_assignment PIN_U22 -to oSEG3[5]
	set_location_assignment PIN_W24 -to oSEG3[6]
	set_location_assignment PIN_G26 -to key_mult
	set_location_assignment PIN_P23 -to key_yflag
	set_location_assignment PIN_W26 -to key_xflag
	set_location_assignment PIN_N2 -to clk
	set_location_assignment PIN_V2 -to rst_n
	set_location_assignment PIN_N23 -to key_sum
	set_location_assignment PIN_B13 -to key_switch[8]
	set_location_assignment PIN_A13 -to key_switch[9]
	set_location_assignment PIN_Y18 -to led_data[7]
	set_location_assignment PIN_AA20 -to led_data[6]
	set_location_assignment PIN_U17 -to led_data[5]
	set_location_assignment PIN_U18 -to led_data[4]
	set_location_assignment PIN_V18 -to led_data[3]
	set_location_assignment PIN_W19 -to led_data[2]
	set_location_assignment PIN_AF22 -to led_data[1]
	set_location_assignment PIN_AE22 -to led_data[0]
	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}