{ "Info" "ITDB_TSU_RESULT" "x\[2\] rst_n clk 7.418 ns register " "Info: tsu for register \"x\[2\]\" (data pin = \"rst_n\", clock pin = \"clk\") is 7.418 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.139 ns + Longest pin register " "Info: + Longest pin to register delay is 10.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns rst_n 1 PIN PIN_V2 44 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 44; PIN Node = 'rst_n'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.966 ns) + CELL(0.388 ns) 8.206 ns Decoder0~0 2 COMB LCCOMB_X59_Y20_N8 2 " "Info: 2: + IC(6.966 ns) + CELL(0.388 ns) = 8.206 ns; Loc. = LCCOMB_X59_Y20_N8; Fanout = 2; COMB Node = 'Decoder0~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "7.354 ns" { rst_n Decoder0~0 } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 112 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.388 ns) 8.847 ns Decoder0~1 3 COMB LCCOMB_X59_Y20_N28 4 " "Info: 3: + IC(0.253 ns) + CELL(0.388 ns) = 8.847 ns; Loc. = LCCOMB_X59_Y20_N28; Fanout = 4; COMB Node = 'Decoder0~1'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.641 ns" { Decoder0~0 Decoder0~1 } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 112 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.632 ns) + CELL(0.660 ns) 10.139 ns x\[2\] 4 REG LCFF_X57_Y20_N21 13 " "Info: 4: + IC(0.632 ns) + CELL(0.660 ns) = 10.139 ns; Loc. = LCFF_X57_Y20_N21; Fanout = 13; REG Node = 'x\[2\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.292 ns" { Decoder0~1 x[2] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.288 ns ( 22.57 % ) " "Info: Total cell delay = 2.288 ns ( 22.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.851 ns ( 77.43 % ) " "Info: Total interconnect delay = 7.851 ns ( 77.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "10.139 ns" { rst_n Decoder0~0 Decoder0~1 x[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "10.139 ns" { rst_n {} rst_n~combout {} Decoder0~0 {} Decoder0~1 {} x[2] {} } { 0.000ns 0.000ns 6.966ns 0.253ns 0.632ns } { 0.000ns 0.852ns 0.388ns 0.388ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.685 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns x\[2\] 3 REG LCFF_X57_Y20_N21 13 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X57_Y20_N21; Fanout = 13; REG Node = 'x\[2\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl x[2] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl x[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.685 ns" { clk {} clk~combout {} clk~clkctrl {} x[2] {} } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "10.139 ns" { rst_n Decoder0~0 Decoder0~1 x[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "10.139 ns" { rst_n {} rst_n~combout {} Decoder0~0 {} Decoder0~1 {} x[2] {} } { 0.000ns 0.000ns 6.966ns 0.253ns 0.632ns } { 0.000ns 0.852ns 0.388ns 0.388ns 0.660ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl x[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.685 ns" { clk {} clk~combout {} clk~clkctrl {} x[2] {} } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk oSEG0\[5\] result_data\[5\] 14.339 ns register " "Info: tco from clock \"clk\" to destination pin \"oSEG0\[5\]\" through register \"result_data\[5\]\" is 14.339 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.685 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.537 ns) 2.685 ns result_data\[5\] 3 REG LCFF_X56_Y20_N25 23 " "Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X56_Y20_N25; Fanout = 23; REG Node = 'result_data\[5\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.568 ns" { clk~clkctrl result_data[5] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl result_data[5] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.685 ns" { clk {} clk~combout {} clk~clkctrl {} result_data[5] {} } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.404 ns + Longest register pin " "Info: + Longest register to pin delay is 11.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns result_data\[5\] 1 REG LCFF_X56_Y20_N25 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y20_N25; Fanout = 23; REG Node = 'result_data\[5\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { result_data[5] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.438 ns) 1.552 ns comb~25 2 COMB LCCOMB_X57_Y19_N12 1 " "Info: 2: + IC(1.114 ns) + CELL(0.438 ns) = 1.552 ns; Loc. = LCCOMB_X57_Y19_N12; Fanout = 1; COMB Node = 'comb~25'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.552 ns" { result_data[5] comb~25 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.269 ns) + CELL(0.437 ns) 2.258 ns comb~20 3 COMB LCCOMB_X57_Y19_N18 1 " "Info: 3: + IC(0.269 ns) + CELL(0.437 ns) = 2.258 ns; Loc. = LCCOMB_X57_Y19_N18; Fanout = 1; COMB Node = 'comb~20'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.706 ns" { comb~25 comb~20 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.419 ns) 2.936 ns comb~35 4 COMB LCCOMB_X57_Y19_N6 1 " "Info: 4: + IC(0.259 ns) + CELL(0.419 ns) = 2.936 ns; Loc. = LCCOMB_X57_Y19_N6; Fanout = 1; COMB Node = 'comb~35'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.678 ns" { comb~20 comb~35 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.438 ns) 3.639 ns ge_data\[2\]~34 5 COMB LCCOMB_X57_Y19_N4 7 " "Info: 5: + IC(0.265 ns) + CELL(0.438 ns) = 3.639 ns; Loc. = LCCOMB_X57_Y19_N4; Fanout = 7; COMB Node = 'ge_data\[2\]~34'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.703 ns" { comb~35 ge_data[2]~34 } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.437 ns) 4.820 ns Seg7_lut:u_Seg7_lut0\|WideOr1~0 6 COMB LCCOMB_X55_Y19_N18 1 " "Info: 6: + IC(0.744 ns) + CELL(0.437 ns) = 4.820 ns; Loc. = LCCOMB_X55_Y19_N18; Fanout = 1; COMB Node = 'Seg7_lut:u_Seg7_lut0\|WideOr1~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.181 ns" { ge_data[2]~34 Seg7_lut:u_Seg7_lut0|WideOr1~0 } "NODE_NAME" } } { "../src/seg7_lut.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/seg7_lut.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.796 ns) + CELL(2.788 ns) 11.404 ns oSEG0\[5\] 7 PIN PIN_V14 0 " "Info: 7: + IC(3.796 ns) + CELL(2.788 ns) = 11.404 ns; Loc. = PIN_V14; Fanout = 0; PIN Node = 'oSEG0\[5\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "6.584 ns" { Seg7_lut:u_Seg7_lut0|WideOr1~0 oSEG0[5] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.957 ns ( 43.47 % ) " "Info: Total cell delay = 4.957 ns ( 43.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.447 ns ( 56.53 % ) " "Info: Total interconnect delay = 6.447 ns ( 56.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "11.404 ns" { result_data[5] comb~25 comb~20 comb~35 ge_data[2]~34 Seg7_lut:u_Seg7_lut0|WideOr1~0 oSEG0[5] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "11.404 ns" { result_data[5] {} comb~25 {} comb~20 {} comb~35 {} ge_data[2]~34 {} Seg7_lut:u_Seg7_lut0|WideOr1~0 {} oSEG0[5] {} } { 0.000ns 1.114ns 0.269ns 0.259ns 0.265ns 0.744ns 3.796ns } { 0.000ns 0.438ns 0.437ns 0.419ns 0.438ns 0.437ns 2.788ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.685 ns" { clk clk~clkctrl result_data[5] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.685 ns" { clk {} clk~combout {} clk~clkctrl {} result_data[5] {} } { 0.000ns 0.000ns 0.118ns 1.031ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "11.404 ns" { result_data[5] comb~25 comb~20 comb~35 ge_data[2]~34 Seg7_lut:u_Seg7_lut0|WideOr1~0 oSEG0[5] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "11.404 ns" { result_data[5] {} comb~25 {} comb~20 {} comb~35 {} ge_data[2]~34 {} Seg7_lut:u_Seg7_lut0|WideOr1~0 {} oSEG0[5] {} } { 0.000ns 1.114ns 0.269ns 0.259ns 0.265ns 0.744ns 3.796ns } { 0.000ns 0.438ns 0.437ns 0.419ns 0.438ns 0.437ns 2.788ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "din\[3\] key_switch\[2\] clk 0.343 ns register " "Info: th for register \"din\[3\]\" (data pin = \"key_switch\[2\]\", clock pin = \"clk\") is 0.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.688 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 2.688 ns din\[3\] 3 REG LCFF_X59_Y19_N17 3 " "Info: 3: + IC(1.034 ns) + CELL(0.537 ns) = 2.688 ns; Loc. = LCFF_X59_Y19_N17; Fanout = 3; REG Node = 'din\[3\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.571 ns" { clk~clkctrl din[3] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.14 % ) " "Info: Total cell delay = 1.536 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.152 ns ( 42.86 % ) " "Info: Total interconnect delay = 1.152 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.688 ns" { clk clk~clkctrl din[3] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.688 ns" { clk {} clk~combout {} clk~clkctrl {} din[3] {} } { 0.000ns 0.000ns 0.118ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 49 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.611 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns key_switch\[2\] 1 PIN PIN_P25 6 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 6; PIN Node = 'key_switch\[2\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { key_switch[2] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.275 ns) 2.128 ns Equal9~1 2 COMB LCCOMB_X59_Y19_N28 2 " "Info: 2: + IC(0.854 ns) + CELL(0.275 ns) = 2.128 ns; Loc. = LCCOMB_X59_Y19_N28; Fanout = 2; COMB Node = 'Equal9~1'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.129 ns" { key_switch[2] Equal9~1 } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.149 ns) 2.527 ns Selector0~0 3 COMB LCCOMB_X59_Y19_N16 1 " "Info: 3: + IC(0.250 ns) + CELL(0.149 ns) = 2.527 ns; Loc. = LCCOMB_X59_Y19_N16; Fanout = 1; COMB Node = 'Selector0~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.399 ns" { Equal9~1 Selector0~0 } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.611 ns din\[3\] 4 REG LCFF_X59_Y19_N17 3 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.611 ns; Loc. = LCFF_X59_Y19_N17; Fanout = 3; REG Node = 'din\[3\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector0~0 din[3] } "NODE_NAME" } } { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.507 ns ( 57.72 % ) " "Info: Total cell delay = 1.507 ns ( 57.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.104 ns ( 42.28 % ) " "Info: Total interconnect delay = 1.104 ns ( 42.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.611 ns" { key_switch[2] Equal9~1 Selector0~0 din[3] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.611 ns" { key_switch[2] {} key_switch[2]~combout {} Equal9~1 {} Selector0~0 {} din[3] {} } { 0.000ns 0.000ns 0.854ns 0.250ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.688 ns" { clk clk~clkctrl din[3] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.688 ns" { clk {} clk~combout {} clk~clkctrl {} din[3] {} } { 0.000ns 0.000ns 0.118ns 1.034ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.611 ns" { key_switch[2] Equal9~1 Selector0~0 din[3] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.611 ns" { key_switch[2] {} key_switch[2]~combout {} Equal9~1 {} Selector0~0 {} din[3] {} } { 0.000ns 0.000ns 0.854ns 0.250ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}