Quartus II 64-Bit
Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
11
1000
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
key_scan
# storage
db|Calculator_Design.(1).cnf
db|Calculator_Design.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|altera_project|labtest|calculator_design|src|key_scan.v
471fcc79a15c13674a9426a53dfd2f65
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
KEY_WIDTH
4
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
key_scan:u_key_scan
}
# macro_sequence

# end
# entity
adder_4bits
# storage
db|Calculator_Design.(2).cnf
db|Calculator_Design.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|altera_project|labtest|calculator_design|src|adder_4bits.v
f6e63dde2b7d690236d378860b953b
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
adder_4bits:u_adder_4bits
}
# macro_sequence

# end
# entity
Seg7_lut
# storage
db|Calculator_Design.(4).cnf
db|Calculator_Design.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|altera_project|labtest|calculator_design|src|seg7_lut.v
5e9288f1f3939f225f7b541e287ee24f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Seg7_lut:u_Seg7_lut3
Seg7_lut:u_Seg7_lut2
Seg7_lut:u_Seg7_lut1
Seg7_lut:u_Seg7_lut0
}
# macro_sequence

# end
# entity
mult_4bits
# storage
db|Calculator_Design.(3).cnf
db|Calculator_Design.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|altera_project|labtest|calculator_design|src|mult_4bits.v
ed648d9750b27e1c69b99cfb1c86832f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
mult_4bits:u_mult_4bits
}
# macro_sequence

# end
# entity
Calculator_Design
# storage
db|Calculator_Design.(0).cnf
db|Calculator_Design.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|altera_project|labtest|calculator_design|src|calculator_design.v
bc45941ef5d0cd29493ca32cd527875
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# complete