# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
# Date created = 21:46:40  November 01, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		Labtest_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C8
set_global_assignment -name TOP_LEVEL_ENTITY Labtest
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:46:40  NOVEMBER 01, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_location_assignment PIN_N2 -to clk
set_location_assignment PIN_V2 -to rst_n
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AF10 -to oSEG0[0]
set_location_assignment PIN_AB12 -to oSEG0[1]
set_location_assignment PIN_AC12 -to oSEG0[2]
set_location_assignment PIN_AD11 -to oSEG0[3]
set_location_assignment PIN_AE11 -to oSEG0[4]
set_location_assignment PIN_V14 -to oSEG0[5]
set_location_assignment PIN_V13 -to oSEG0[6]
set_location_assignment PIN_V20 -to oSEG1[0]
set_location_assignment PIN_V21 -to oSEG1[1]
set_location_assignment PIN_W21 -to oSEG1[2]
set_location_assignment PIN_Y22 -to oSEG1[3]
set_location_assignment PIN_AA24 -to oSEG1[4]
set_location_assignment PIN_AA23 -to oSEG1[5]
set_location_assignment PIN_AB24 -to oSEG1[6]
set_location_assignment PIN_AB23 -to oSEG2[0]
set_location_assignment PIN_V22 -to oSEG2[1]
set_location_assignment PIN_AC25 -to oSEG2[2]
set_location_assignment PIN_AC26 -to oSEG2[3]
set_location_assignment PIN_AB26 -to oSEG2[4]
set_location_assignment PIN_AB25 -to oSEG2[5]
set_location_assignment PIN_Y24 -to oSEG2[6]
set_location_assignment PIN_Y23 -to oSEG3[0]
set_location_assignment PIN_AA25 -to oSEG3[1]
set_location_assignment PIN_AA26 -to oSEG3[2]
set_location_assignment PIN_Y26 -to oSEG3[3]
set_location_assignment PIN_Y25 -to oSEG3[4]
set_location_assignment PIN_U22 -to oSEG3[5]
set_location_assignment PIN_W24 -to oSEG3[6]
set_global_assignment -name MISC_FILE "D:/Altera_Project/Labtest/Labtest.dpf"
set_global_assignment -name VERILOG_FILE seg7_lut.v
set_global_assignment -name VERILOG_FILE time_counter.v
set_global_assignment -name VERILOG_FILE led_display.v
set_global_assignment -name VERILOG_FILE Labtest.v
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top