; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+------------------------+------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path             ;
+----------------------------------+-----------------+------------------------+------------------------------------------+
; seg7_lut.v                       ; yes             ; User Verilog HDL File  ; D:/Altera_Project/Labtest/seg7_lut.v     ;
; time_counter.v                   ; yes             ; User Verilog HDL File  ; D:/Altera_Project/Labtest/time_counter.v ;
; Labtest.v                        ; yes             ; User Verilog HDL File  ; D:/Altera_Project/Labtest/Labtest.v      ;
+----------------------------------+-----------------+------------------------+------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 179   ;
;                                             ;       ;
; Total combinational functions               ; 179   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 90    ;
;     -- 3 input functions                    ; 30    ;
;     -- <=2 input functions                  ; 59    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 131   ;
;     -- arithmetic mode                      ; 48    ;
;                                             ;       ;
; Total registers                             ; 52    ;
;     -- Dedicated logic registers            ; 52    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 30    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 52    ;
; Total fan-out                               ; 802   ;
; Average fan-out                             ; 3.07  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
; Compilation Hierarchy Node       ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                  ; Library Name ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
; |Labtest                         ; 179 (0)           ; 52 (0)       ; 0           ; 0            ; 0       ; 0         ; 30   ; 0            ; |Labtest                             ; work         ;
;    |Seg7_lut:u_Seg7_lut0|        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Labtest|Seg7_lut:u_Seg7_lut0        ;              ;
;    |Seg7_lut:u_Seg7_lut1|        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Labtest|Seg7_lut:u_Seg7_lut1        ;              ;
;    |Seg7_lut:u_Seg7_lut2|        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Labtest|Seg7_lut:u_Seg7_lut2        ;              ;
;    |Seg7_lut:u_Seg7_lut3|        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Labtest|Seg7_lut:u_Seg7_lut3        ;              ;
;    |time_counter:u_time_counter| ; 151 (151)         ; 52 (52)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Labtest|time_counter:u_time_counter ;              ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 52    ;
; Number of registers using Synchronous Clear  ; 38    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 52    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |Labtest|time_counter:u_time_counter|sec[3]   ;
; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |Labtest|time_counter:u_time_counter|min[3]   ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Labtest|time_counter:u_time_counter|min_h[1] ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Labtest|time_counter:u_time_counter|sec_h[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+


+--------------------------------------------------+
; Port Connectivity Checks: "Seg7_lut:u_Seg7_lut1" ;
+---------+-------+----------+---------------------+
; Port    ; Type  ; Severity ; Details             ;
+---------+-------+----------+---------------------+
; iDIG[3] ; Input ; Info     ; Stuck at GND        ;
+---------+-------+----------+---------------------+


+--------------------------------------------------+
; Port Connectivity Checks: "Seg7_lut:u_Seg7_lut3" ;
+---------+-------+----------+---------------------+
; Port    ; Type  ; Severity ; Details             ;
+---------+-------+----------+---------------------+
; iDIG[3] ; Input ; Info     ; Stuck at GND        ;
+---------+-------+----------+---------------------+


+---------------------------------------------------------+
; Port Connectivity Checks: "time_counter:u_time_counter" ;
+-------+--------+----------+-----------------------------+
; Port  ; Type   ; Severity ; Details                     ;
+-------+--------+----------+-----------------------------+
; mse_h ; Output ; Info     ; Explicitly unconnected      ;
; mse_b ; Output ; Info     ; Explicitly unconnected      ;
; mse_l ; Output ; Info     ; Explicitly unconnected      ;
+-------+--------+----------+-----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 01 23:00:53 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Labtest -c Labtest
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file seg7_lut.v
    Info: Found entity 1: Seg7_lut
Info: Found 1 design units, including 1 entities, in source file time_counter.v
    Info: Found entity 1: time_counter
Info: Found 1 design units, including 1 entities, in source file led_display.v
    Info: Found entity 1: led_display
Info: Found 1 design units, including 1 entities, in source file labtest.v
    Info: Found entity 1: Labtest
Info: Elaborating entity "Labtest" for the top level hierarchy
Info: Elaborating entity "time_counter" for hierarchy "time_counter:u_time_counter"
Info: Elaborating entity "Seg7_lut" for hierarchy "Seg7_lut:u_Seg7_lut3"
Info: Implemented 209 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 28 output pins
    Info: Implemented 179 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 266 megabytes
    Info: Processing ended: Thu Nov 01 23:00:54 2012
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:02