Quartus II 64-Bit
Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
11
1004
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
led_display
# storage
db|Labtest.(0).cnf
db|Labtest.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
led_display.v
b7c4c59cd6993f71d6ed53b49e19bf
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
lpm_divide
# storage
db|Labtest.(2).cnf
db|Labtest.(2).cnf
# case_insensitive
# source_file
c:|altera|91|quartus|libraries|megafunctions|lpm_divide.tdf
b5df2a3096cc60b7f67ac02ee1d0ff6a
7
# user_parameter {
LPM_WIDTHN
10
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
7
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_g6m
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain6
-1
3
remain5
-1
3
remain4
-1
3
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer9
-1
3
numer8
-1
3
numer7
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom4
-1
1
denom3
-1
1
denom1
-1
1
denom0
-1
1
denom6
-1
2
denom5
-1
2
denom2
-1
2
}
# macro_sequence

# end
# entity
lpm_divide_g6m
# storage
db|Labtest.(3).cnf
db|Labtest.(3).cnf
# case_insensitive
# source_file
db|lpm_divide_g6m.tdf
c7c1ffdc1ce24b1e48e855c9fbfe3dbf
7
# used_port {
remain6
-1
3
remain5
-1
3
remain4
-1
3
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer9
-1
3
numer8
-1
3
numer7
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom6
-1
3
denom5
-1
3
denom4
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# macro_sequence

# end
# entity
sign_div_unsign_nlh
# storage
db|Labtest.(4).cnf
db|Labtest.(4).cnf
# case_insensitive
# source_file
db|sign_div_unsign_nlh.tdf
9f5c71ede15ac6852e543b978ea2814f
7
# used_port {
remainder6
-1
3
remainder5
-1
3
remainder4
-1
3
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient9
-1
3
quotient8
-1
3
quotient7
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator9
-1
3
numerator8
-1
3
numerator7
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator6
-1
3
denominator5
-1
3
denominator4
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
alt_u_div_g2f
# storage
db|Labtest.(5).cnf
db|Labtest.(5).cnf
# case_insensitive
# source_file
db|alt_u_div_g2f.tdf
892f7ba5bd73c9caa5a835f71779a3e
7
# used_port {
remainder6
-1
3
remainder5
-1
3
remainder4
-1
3
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient9
-1
3
quotient8
-1
3
quotient7
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator9
-1
3
numerator8
-1
3
numerator7
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator6
-1
3
denominator5
-1
3
denominator4
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
add_sub_lkc
# storage
db|Labtest.(6).cnf
db|Labtest.(6).cnf
# case_insensitive
# source_file
db|add_sub_lkc.tdf
9cbc60ebeaf9f9c821d1cfe83579ead
7
# used_port {
result0
-1
3
datab0
-1
3
dataa0
-1
3
cout
-1
3
}
# macro_sequence

# end
# entity
add_sub_mkc
# storage
db|Labtest.(7).cnf
db|Labtest.(7).cnf
# case_insensitive
# source_file
db|add_sub_mkc.tdf
f368ce1c97d7d96e53c31ea2f4d43475
7
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# macro_sequence

# end
# entity
lpm_divide
# storage
db|Labtest.(8).cnf
db|Labtest.(8).cnf
# case_insensitive
# source_file
c:|altera|91|quartus|libraries|megafunctions|lpm_divide.tdf
b5df2a3096cc60b7f67ac02ee1d0ff6a
7
# user_parameter {
LPM_WIDTHN
7
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_0dm
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# macro_sequence

# end
# entity
lpm_divide_0dm
# storage
db|Labtest.(9).cnf
db|Labtest.(9).cnf
# case_insensitive
# source_file
db|lpm_divide_0dm.tdf
e2dc8cf783dcb894f4dcc5f347da2971
7
# used_port {
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# macro_sequence

# end
# entity
sign_div_unsign_akh
# storage
db|Labtest.(10).cnf
db|Labtest.(10).cnf
# case_insensitive
# source_file
db|sign_div_unsign_akh.tdf
309b33c453b2a1f655edb078a62e213b
7
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
alt_u_div_mve
# storage
db|Labtest.(11).cnf
db|Labtest.(11).cnf
# case_insensitive
# source_file
db|alt_u_div_mve.tdf
8b2611bc631c5e29f5822e8318b76cb
7
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
lpm_divide
# storage
db|Labtest.(12).cnf
db|Labtest.(12).cnf
# case_insensitive
# source_file
c:|altera|91|quartus|libraries|megafunctions|lpm_divide.tdf
b5df2a3096cc60b7f67ac02ee1d0ff6a
7
# user_parameter {
LPM_WIDTHN
10
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
4
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_d6m
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer9
-1
3
numer8
-1
3
numer7
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
1
denom0
-1
1
denom3
-1
2
denom1
-1
2
}
# macro_sequence

# end
# entity
lpm_divide_d6m
# storage
db|Labtest.(13).cnf
db|Labtest.(13).cnf
# case_insensitive
# source_file
db|lpm_divide_d6m.tdf
d993c93a4d88fddba3dd14ecd6be9ad
7
# used_port {
remain3
-1
3
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer9
-1
3
numer8
-1
3
numer7
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# macro_sequence

# end
# entity
sign_div_unsign_klh
# storage
db|Labtest.(14).cnf
db|Labtest.(14).cnf
# case_insensitive
# source_file
db|sign_div_unsign_klh.tdf
1aa4e16522ed66020a8c285cee5fb63
7
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient9
-1
3
quotient8
-1
3
quotient7
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator9
-1
3
numerator8
-1
3
numerator7
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
alt_u_div_a2f
# storage
db|Labtest.(15).cnf
db|Labtest.(15).cnf
# case_insensitive
# source_file
db|alt_u_div_a2f.tdf
c832cc67ca9d7188fb88d434fba6e7b7
7
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient9
-1
3
quotient8
-1
3
quotient7
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator9
-1
3
numerator8
-1
3
numerator7
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# macro_sequence

# end
# entity
Labtest
# storage
db|Labtest.(1).cnf
db|Labtest.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
labtest.v
a054d44950defc446675ad159078cd88
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
Seg7_lut
# storage
db|Labtest.(17).cnf
db|Labtest.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
seg7_lut.v
5e9288f1f3939f225f7b541e287ee24f
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
Seg7_lut:u_Seg7_lut3
Seg7_lut:u_Seg7_lut2
Seg7_lut:u_Seg7_lut1
Seg7_lut:u_Seg7_lut0
}
# macro_sequence

# end
# entity
time_counter
# storage
db|Labtest.(16).cnf
db|Labtest.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
time_counter.v
32cba052fcdc91b5c8f4925b5d92c96b
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
time_counter:u_time_counter
}
# macro_sequence

# end
# complete