{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Labtest -c Labtest " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Labtest -c Labtest" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Info: Peak virtual memory: 304 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 01 22:56:58 2012 " "Info: Processing ended: Thu Nov 01 22:56:58 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 01 22:56:59 2012 " "Info: Processing started: Thu Nov 01 22:56:59 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Labtest -c Labtest --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Labtest -c Labtest --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } } { "c:/altera/91/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register time_counter:u_time_counter\|cnt\[17\] register time_counter:u_time_counter\|sec\[1\] 140.41 MHz 7.122 ns Internal " "Info: Clock \"clk\" has Internal fmax of 140.41 MHz between source register \"time_counter:u_time_counter\|cnt\[17\]\" and destination register \"time_counter:u_time_counter\|sec\[1\]\" (period= 7.122 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.849 ns + Longest register register " "Info: + Longest register to register delay is 6.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_counter:u_time_counter\|cnt\[17\] 1 REG LCFF_X46_Y15_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y15_N7; Fanout = 3; REG Node = 'time_counter:u_time_counter\|cnt\[17\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { time_counter:u_time_counter|cnt[17] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.534 ns) 1.572 ns time_counter:u_time_counter\|Equal0~0 2 COMB LCCOMB_X45_Y15_N0 2 " "Info: 2: + IC(1.038 ns) + CELL(0.534 ns) = 1.572 ns; Loc. = LCCOMB_X45_Y15_N0; Fanout = 2; COMB Node = 'time_counter:u_time_counter\|Equal0~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.572 ns" { time_counter:u_time_counter|cnt[17] time_counter:u_time_counter|Equal0~0 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.614 ns) 3.300 ns time_counter:u_time_counter\|Equal0~4 3 COMB LCCOMB_X45_Y16_N10 1 " "Info: 3: + IC(1.114 ns) + CELL(0.614 ns) = 3.300 ns; Loc. = LCCOMB_X45_Y16_N10; Fanout = 1; COMB Node = 'time_counter:u_time_counter\|Equal0~4'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.728 ns" { time_counter:u_time_counter|Equal0~0 time_counter:u_time_counter|Equal0~4 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.614 ns) 4.306 ns time_counter:u_time_counter\|Equal0~8 4 COMB LCCOMB_X45_Y16_N28 12 " "Info: 4: + IC(0.392 ns) + CELL(0.614 ns) = 4.306 ns; Loc. = LCCOMB_X45_Y16_N28; Fanout = 12; COMB Node = 'time_counter:u_time_counter\|Equal0~8'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.006 ns" { time_counter:u_time_counter|Equal0~4 time_counter:u_time_counter|Equal0~8 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.206 ns) 4.906 ns time_counter:u_time_counter\|sec\[4\]~0 5 COMB LCCOMB_X45_Y16_N6 7 " "Info: 5: + IC(0.394 ns) + CELL(0.206 ns) = 4.906 ns; Loc. = LCCOMB_X45_Y16_N6; Fanout = 7; COMB Node = 'time_counter:u_time_counter\|sec\[4\]~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.600 ns" { time_counter:u_time_counter|Equal0~8 time_counter:u_time_counter|sec[4]~0 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.855 ns) 6.849 ns time_counter:u_time_counter\|sec\[1\] 6 REG LCFF_X45_Y13_N25 15 " "Info: 6: + IC(1.088 ns) + CELL(0.855 ns) = 6.849 ns; Loc. = LCFF_X45_Y13_N25; Fanout = 15; REG Node = 'time_counter:u_time_counter\|sec\[1\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.943 ns" { time_counter:u_time_counter|sec[4]~0 time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.823 ns ( 41.22 % ) " "Info: Total cell delay = 2.823 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.026 ns ( 58.78 % ) " "Info: Total interconnect delay = 4.026 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "6.849 ns" { time_counter:u_time_counter|cnt[17] time_counter:u_time_counter|Equal0~0 time_counter:u_time_counter|Equal0~4 time_counter:u_time_counter|Equal0~8 time_counter:u_time_counter|sec[4]~0 time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "6.849 ns" { time_counter:u_time_counter|cnt[17] {} time_counter:u_time_counter|Equal0~0 {} time_counter:u_time_counter|Equal0~4 {} time_counter:u_time_counter|Equal0~8 {} time_counter:u_time_counter|sec[4]~0 {} time_counter:u_time_counter|sec[1] {} } { 0.000ns 1.038ns 1.114ns 0.392ns 0.394ns 1.088ns } { 0.000ns 0.534ns 0.614ns 0.614ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.197 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 3.197 ns time_counter:u_time_counter\|sec\[1\] 3 REG LCFF_X45_Y13_N25 15 " "Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.197 ns; Loc. = LCFF_X45_Y13_N25; Fanout = 15; REG Node = 'time_counter:u_time_counter\|sec\[1\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.848 ns" { clk~clkctrl time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.55 % ) " "Info: Total cell delay = 1.776 ns ( 55.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.421 ns ( 44.45 % ) " "Info: Total interconnect delay = 1.421 ns ( 44.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.197 ns" { clk clk~clkctrl time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.197 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|sec[1] {} } { 0.000ns 0.000ns 0.239ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.206 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.666 ns) 3.206 ns time_counter:u_time_counter\|cnt\[17\] 3 REG LCFF_X46_Y15_N7 3 " "Info: 3: + IC(1.191 ns) + CELL(0.666 ns) = 3.206 ns; Loc. = LCFF_X46_Y15_N7; Fanout = 3; REG Node = 'time_counter:u_time_counter\|cnt\[17\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.857 ns" { clk~clkctrl time_counter:u_time_counter|cnt[17] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.40 % ) " "Info: Total cell delay = 1.776 ns ( 55.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.430 ns ( 44.60 % ) " "Info: Total interconnect delay = 1.430 ns ( 44.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.206 ns" { clk clk~clkctrl time_counter:u_time_counter|cnt[17] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.206 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|cnt[17] {} } { 0.000ns 0.000ns 0.239ns 1.191ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.197 ns" { clk clk~clkctrl time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.197 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|sec[1] {} } { 0.000ns 0.000ns 0.239ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.206 ns" { clk clk~clkctrl time_counter:u_time_counter|cnt[17] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.206 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|cnt[17] {} } { 0.000ns 0.000ns 0.239ns 1.191ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "6.849 ns" { time_counter:u_time_counter|cnt[17] time_counter:u_time_counter|Equal0~0 time_counter:u_time_counter|Equal0~4 time_counter:u_time_counter|Equal0~8 time_counter:u_time_counter|sec[4]~0 time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "6.849 ns" { time_counter:u_time_counter|cnt[17] {} time_counter:u_time_counter|Equal0~0 {} time_counter:u_time_counter|Equal0~4 {} time_counter:u_time_counter|Equal0~8 {} time_counter:u_time_counter|sec[4]~0 {} time_counter:u_time_counter|sec[1] {} } { 0.000ns 1.038ns 1.114ns 0.392ns 0.394ns 1.088ns } { 0.000ns 0.534ns 0.614ns 0.614ns 0.206ns 0.855ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.197 ns" { clk clk~clkctrl time_counter:u_time_counter|sec[1] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.197 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|sec[1] {} } { 0.000ns 0.000ns 0.239ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.206 ns" { clk clk~clkctrl time_counter:u_time_counter|cnt[17] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.206 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|cnt[17] {} } { 0.000ns 0.000ns 0.239ns 1.191ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk oSEG2\[0\] time_counter:u_time_counter\|min\[2\] 17.381 ns register " "Info: tco from clock \"clk\" to destination pin \"oSEG2\[0\]\" through register \"time_counter:u_time_counter\|min\[2\]\" is 17.381 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.202 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.666 ns) 3.202 ns time_counter:u_time_counter\|min\[2\] 3 REG LCFF_X45_Y14_N23 16 " "Info: 3: + IC(1.187 ns) + CELL(0.666 ns) = 3.202 ns; Loc. = LCFF_X45_Y14_N23; Fanout = 16; REG Node = 'time_counter:u_time_counter\|min\[2\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.853 ns" { clk~clkctrl time_counter:u_time_counter|min[2] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.47 % ) " "Info: Total cell delay = 1.776 ns ( 55.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.426 ns ( 44.53 % ) " "Info: Total interconnect delay = 1.426 ns ( 44.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.202 ns" { clk clk~clkctrl time_counter:u_time_counter|min[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.202 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|min[2] {} } { 0.000ns 0.000ns 0.239ns 1.187ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.875 ns + Longest register pin " "Info: + Longest register to pin delay is 13.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_counter:u_time_counter\|min\[2\] 1 REG LCFF_X45_Y14_N23 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y14_N23; Fanout = 16; REG Node = 'time_counter:u_time_counter\|min\[2\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { time_counter:u_time_counter|min[2] } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.647 ns) 1.841 ns time_counter:u_time_counter\|LessThan4~0 2 COMB LCCOMB_X45_Y14_N0 2 " "Info: 2: + IC(1.194 ns) + CELL(0.647 ns) = 1.841 ns; Loc. = LCCOMB_X45_Y14_N0; Fanout = 2; COMB Node = 'time_counter:u_time_counter\|LessThan4~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.841 ns" { time_counter:u_time_counter|min[2] time_counter:u_time_counter|LessThan4~0 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.647 ns) 3.591 ns time_counter:u_time_counter\|LessThan4~1 3 COMB LCCOMB_X46_Y12_N8 3 " "Info: 3: + IC(1.103 ns) + CELL(0.647 ns) = 3.591 ns; Loc. = LCCOMB_X46_Y12_N8; Fanout = 3; COMB Node = 'time_counter:u_time_counter\|LessThan4~1'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.750 ns" { time_counter:u_time_counter|LessThan4~0 time_counter:u_time_counter|LessThan4~1 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.202 ns) 4.888 ns time_counter:u_time_counter\|min_l\[2\]~25 4 COMB LCCOMB_X46_Y14_N6 1 " "Info: 4: + IC(1.095 ns) + CELL(0.202 ns) = 4.888 ns; Loc. = LCCOMB_X46_Y14_N6; Fanout = 1; COMB Node = 'time_counter:u_time_counter\|min_l\[2\]~25'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.297 ns" { time_counter:u_time_counter|LessThan4~1 time_counter:u_time_counter|min_l[2]~25 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.651 ns) 5.988 ns time_counter:u_time_counter\|min_l\[2\]~30 5 COMB LCCOMB_X46_Y14_N14 7 " "Info: 5: + IC(0.449 ns) + CELL(0.651 ns) = 5.988 ns; Loc. = LCCOMB_X46_Y14_N14; Fanout = 7; COMB Node = 'time_counter:u_time_counter\|min_l\[2\]~30'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.100 ns" { time_counter:u_time_counter|min_l[2]~25 time_counter:u_time_counter|min_l[2]~30 } "NODE_NAME" } } { "time_counter.v" "" { Text "D:/Altera_Project/Labtest/time_counter.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.370 ns) 6.777 ns Seg7_lut:u_Seg7_lut2\|WideOr6~0 6 COMB LCCOMB_X46_Y14_N16 1 " "Info: 6: + IC(0.419 ns) + CELL(0.370 ns) = 6.777 ns; Loc. = LCCOMB_X46_Y14_N16; Fanout = 1; COMB Node = 'Seg7_lut:u_Seg7_lut2\|WideOr6~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.789 ns" { time_counter:u_time_counter|min_l[2]~30 Seg7_lut:u_Seg7_lut2|WideOr6~0 } "NODE_NAME" } } { "seg7_lut.v" "" { Text "D:/Altera_Project/Labtest/seg7_lut.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.032 ns) + CELL(3.066 ns) 13.875 ns oSEG2\[0\] 7 PIN PIN_AB23 0 " "Info: 7: + IC(4.032 ns) + CELL(3.066 ns) = 13.875 ns; Loc. = PIN_AB23; Fanout = 0; PIN Node = 'oSEG2\[0\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "7.098 ns" { Seg7_lut:u_Seg7_lut2|WideOr6~0 oSEG2[0] } "NODE_NAME" } } { "Labtest.v" "" { Text "D:/Altera_Project/Labtest/Labtest.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.583 ns ( 40.24 % ) " "Info: Total cell delay = 5.583 ns ( 40.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.292 ns ( 59.76 % ) " "Info: Total interconnect delay = 8.292 ns ( 59.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "13.875 ns" { time_counter:u_time_counter|min[2] time_counter:u_time_counter|LessThan4~0 time_counter:u_time_counter|LessThan4~1 time_counter:u_time_counter|min_l[2]~25 time_counter:u_time_counter|min_l[2]~30 Seg7_lut:u_Seg7_lut2|WideOr6~0 oSEG2[0] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "13.875 ns" { time_counter:u_time_counter|min[2] {} time_counter:u_time_counter|LessThan4~0 {} time_counter:u_time_counter|LessThan4~1 {} time_counter:u_time_counter|min_l[2]~25 {} time_counter:u_time_counter|min_l[2]~30 {} Seg7_lut:u_Seg7_lut2|WideOr6~0 {} oSEG2[0] {} } { 0.000ns 1.194ns 1.103ns 1.095ns 0.449ns 0.419ns 4.032ns } { 0.000ns 0.647ns 0.647ns 0.202ns 0.651ns 0.370ns 3.066ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.202 ns" { clk clk~clkctrl time_counter:u_time_counter|min[2] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.202 ns" { clk {} clk~combout {} clk~clkctrl {} time_counter:u_time_counter|min[2] {} } { 0.000ns 0.000ns 0.239ns 1.187ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "13.875 ns" { time_counter:u_time_counter|min[2] time_counter:u_time_counter|LessThan4~0 time_counter:u_time_counter|LessThan4~1 time_counter:u_time_counter|min_l[2]~25 time_counter:u_time_counter|min_l[2]~30 Seg7_lut:u_Seg7_lut2|WideOr6~0 oSEG2[0] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "13.875 ns" { time_counter:u_time_counter|min[2] {} time_counter:u_time_counter|LessThan4~0 {} time_counter:u_time_counter|LessThan4~1 {} time_counter:u_time_counter|min_l[2]~25 {} time_counter:u_time_counter|min_l[2]~30 {} Seg7_lut:u_Seg7_lut2|WideOr6~0 {} oSEG2[0] {} } { 0.000ns 1.194ns 1.103ns 1.095ns 0.449ns 0.419ns 4.032ns } { 0.000ns 0.647ns 0.647ns 0.202ns 0.651ns 0.370ns 3.066ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II 64-Bit " "Info: Quartus II 64-Bit Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "216 " "Info: Peak virtual memory: 216 megabytes" {  } {