1:	mov		0x18, %g3	ldxa		[%g3] ASI_UDBL_ERROR_R, %g3	and		%g3, 0x3ff, %g7		! Paranoia	sllx		%g7, SFSTAT_UDBL_SHIFT, %g7	or		%g4, %g7, %g4	andcc		%g3, %g1, %g3		! UDBE_UE or UDBE_CE	be,pn		%xcc, 1f	 nop	mov		0x18, %g7	stxa		%g3, [%g7] ASI_UDB_ERROR_W	membar		#Sync1:	/* Ok, now that we've latched the error state,	 * clear the sticky bits in the AFSR.	 */	stxa		%g4, [%g0] ASI_AFSR	membar		#Sync	rdpr		%tl, %g2	cmp		%g2, 1	rdpr		%pil, %g2	bleu,pt		%xcc, 1f	 wrpr		%g0, 15, %pil	ba,pt		%xcc, etraptl1	 rd		%pc, %g7	ba,pt		%xcc, 2f	 nop1:	ba,pt		%xcc, etrap_irq	 rd		%pc, %g72:	mov		%l4, %o1	mov		%l5, %o2	call		spitfire_access_error	 add		%sp, PTREGS_OFF, %o0	ba,pt		%xcc, rtrap	 clr		%l6	/* This is the trap handler entry point for ECC correctable	 * errors.  They are corrected, but we listen for the trap	 * so that the event can be logged.	 *	 * Disrupting errors are either:	 * 1) single-bit ECC errors during UDB reads to system	 *    memory	 * 2) data parity errors during write-back events	 *	 * As far as I can make out from the manual, the CEE trap	 * is only for correctable errors during memory read	 * accesses by the front-end of the processor.	 *	 * The code below is only for trap level 1 CEE events,	 * as it is the only situation where we can safely record	 * and log.  For trap level >1 we just clear the CE bit	 * in the AFSR and return.	 *	 * This is just like __spiftire_access_error above, but it	 * specifically handles correctable errors.  If an	 * uncorrectable error is indicated in the AFSR we	 * will branch directly above to __spitfire_access_error	 * to handle it instead.  Uncorrectable therefore takes	 * priority over correctable, and the error logging	 * C code will notice this case by inspecting the	 * trap type.	 */	.globl		__spitfire_cee_trap__spitfire_cee_trap:	ldxa		[%g0] ASI_AFSR, %g4	! Get AFSR	mov		1, %g3	sllx		%g3, SFAFSR_UE_SHIFT, %g3	andcc		%g4, %g3, %g0		! Check for UE	bne,pn		%xcc, __spitfire_access_error	 nop	/* Ok, in this case we only have a correctable error.	 * Indicate we only wish to capture that state in register	 * %g1, and we only disable CE error reporting unlike UE	 * handling which disables all errors.	 */	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g3	andn		%g3, ESTATE_ERR_CE, %g3	stxa		%g3, [%g0] ASI_ESTATE_ERROR_EN	membar		#Sync	/* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */	ba,pt		%xcc, __spitfire_cee_trap_continue	 mov		UDBE_CE, %g1	.globl		__spitfire_data_access_exception	.globl		__spitfire_data_access_exception_tl1__spitfire_data_access_exception_tl1:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit	membar		#Sync	rdpr		%tt, %g3	cmp		%g3, 0x80		! first win spill/fill trap	blu,pn		%xcc, 1f	 cmp		%g3, 0xff		! last win spill/fill trap	bgu,pn		%xcc, 1f	 nop	ba,pt		%xcc, winfix_dax	 rdpr		%tpc, %g31:	sethi		%hi(109f), %g7	ba,pt		%xcc, etraptl1109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		spitfire_data_access_exception_tl1	 add		%sp, PTREGS_OFF, %o0	ba,pt		%xcc, rtrap	 clr		%l6__spitfire_data_access_exception:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etrap109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		spitfire_data_access_exception	 add		%sp, PTREGS_OFF, %o0	ba,pt		%xcc, rtrap	 clr		%l6	.globl		__spitfire_insn_access_exception	.globl		__spitfire_insn_access_exception_tl1__spitfire_insn_access_exception_tl1:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR	rdpr		%tpc, %g5		! IMMU has no SFAR, use TPC	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etraptl1109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		spitfire_insn_access_exception_tl1	 add		%sp, PTREGS_OFF, %o0	ba,pt		%xcc, rtrap	 clr		%l6__spitfire_insn_access_exception:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR	rdpr		%tpc, %g5		! IMMU has no SFAR, use TPC	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etrap109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		spitfire_insn_access_exception	 add		%sp, PTREGS_OFF, %o0	ba,pt		%xcc, rtrap	 clr		%l6	/* These get patched into the trap table at boot time	 * once we know we have a cheetah processor.	 */	.globl		cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1cheetah_fecc_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_DC | DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_fast_ecc), %g2	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0	 mov		0, %g1cheetah_fecc_trap_vector_tl1:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_DC | DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_fast_ecc), %g2	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0	 mov		1, %g1	.globl	cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1cheetah_cee_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_cee), %g2	jmpl		%g2 + %lo(cheetah_cee), %g0	 mov		0, %g1cheetah_cee_trap_vector_tl1:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_cee), %g2	jmpl		%g2 + %lo(cheetah_cee), %g0	 mov		1, %g1	.globl	cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1cheetah_deferred_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;	andn		%g1, DCU_DC | DCU_IC, %g1;	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;	membar		#Sync;	sethi		%hi(cheetah_deferred_trap), %g2	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0	 mov		0, %g1cheetah_deferred_trap_vector_tl1:	membar		#Sync;	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;	andn		%g1, DCU_DC | DCU_IC, %g1;	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;	membar		#Sync;	sethi		%hi(cheetah_deferred_trap), %g2	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0	 mov		1, %g1	/* Cheetah+ specific traps. These are for the new I/D cache parity	 * error traps.  The first argument to cheetah_plus_parity_handler	 * is encoded as follows:	 *	 * Bit0:	0=dcache,1=icache	 * Bit1:	0=recoverable,1=unrecoverable	 */	.globl		cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1cheetah_plus_dcpe_trap_vector:	membar		#Sync	sethi		%hi(do_cheetah_plus_data_parity), %g7	jmpl		%g7 + %lo(do_cheetah_plus_data_parity), %g0	 nop	nop	nop	nop	nopdo_cheetah_plus_data_parity:	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	ba,pt		%xcc, etrap_irq	 rd		%pc, %g7	mov		0x0, %o0	call		cheetah_plus_parity_error	 add		%sp, PTREGS_OFF, %o1	ba,a,pt		%xcc, rtrap_irqcheetah_plus_dcpe_trap_vector_tl1:	membar		#Sync	wrpr		PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate	sethi		%hi(do_dcpe_tl1), %g3	jmpl		%g3 + %lo(do_dcpe_tl1), %g0	 nop	nop	nop	nop	.globl		cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1cheetah_plus_icpe_trap_vector:	membar		#Sync	sethi		%hi(do_cheetah_plus_insn_parity), %g7	jmpl		%g7 + %lo(do_cheetah_plus_insn_parity), %g0	 nop	nop	nop	nop	nopdo_cheetah_plus_insn_parity:	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	ba,pt		%xcc, etrap_irq	 rd		%pc, %g7	mov		0x1, %o0	call		cheetah_plus_parity_error	 add		%sp, PTREGS_OFF, %o1	ba,a,pt		%xcc, rtrap_irqcheetah_plus_icpe_trap_vector_tl1:	membar		#Sync	wrpr		PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate	sethi		%hi(do_icpe_tl1), %g3	jmpl		%g3 + %lo(do_icpe_tl1), %g0	 nop	nop	nop	nop	/* If we take one of these traps when tl >= 1, then we	 * jump to interrupt globals.  If some trap level above us	 * was also using interrupt globals, we cannot recover.	 * We may use all interrupt global registers except %g6.	 */	.globl		do_dcpe_tl1, do_icpe_tl1do_dcpe_tl1:	rdpr		%tl, %g1		! Save original trap level	mov		1, %g2			! Setup TSTATE checking loop	sethi		%hi(TSTATE_IG), %g3	! TSTATE mask bit1:	wrpr		%g2, %tl		! Set trap level to check	rdpr		%tstate, %g4		! Read TSTATE for this level	andcc		%g4, %g3, %g0		! Interrupt globals in use?	bne,a,pn	%xcc, do_dcpe_tl1_fatal	! Yep, irrecoverable	 wrpr		%g1, %tl		! Restore original trap level	add		%g2, 1, %g2		! Next trap level	cmp		%g2, %g1		! Hit them all yet?	ble,pt		%icc, 1b		! Not yet	 nop	wrpr		%g1, %tl		! Restore original trap leveldo_dcpe_tl1_nonfatal:	/* Ok we may use interrupt globals safely. */	sethi		%hi(dcache_parity_tl1_occurred), %g2	lduw		[%g2 + %lo(dcache_parity_tl1_occurred)], %g1	add		%g1, 1, %g1	stw		%g1, [%g2 + %lo(dcache_parity_tl1_occurred)]	/* Reset D-cache parity */	sethi		%hi(1 << 16), %g1	! D-cache size	mov		(1 << 5), %g2		! D-cache line size	sub		%g1, %g2, %g1		! Move down 1 cacheline1:	srl		%g1, 14, %g3		! Compute UTAG	membar		#Sync	stxa		%g3, [%g1] ASI_DCACHE_UTAG	membar		#Sync	sub		%g2, 8, %g3		! 64-bit data word within line2:	membar		#Sync	stxa		%g0, [%g1 + %g3] ASI_DCACHE_DATA	membar		#Sync	subcc		%g3, 8, %g3		! Next 64-bit data word	bge,pt		%icc, 2b	 nop	subcc		%g1, %g2, %g1		! Next cacheline	bge,pt		%icc, 1b	 nop	ba,pt		%xcc, dcpe_icpe_tl1_common	 nopdo_dcpe_tl1_fatal:	sethi		%hi(1f), %g7	ba,pt		%xcc, etraptl11:	or		%g7, %lo(1b), %g7	mov		0x2, %o0	call		cheetah_plus_parity_error	 add		%sp, PTREGS_OFF, %o1	ba,pt		%xcc, rtrap	 clr		%l6do_icpe_tl1:	rdpr		%tl, %g1		! Save original trap level	mov		1, %g2			! Setup TSTATE checking loop	sethi		%hi(TSTATE_IG), %g3	! TSTATE mask bit1:	wrpr		%g2, %tl		! Set trap level to check	rdpr		%tstate, %g4		! Read TSTATE for this level	andcc		%g4, %g3, %g0		! Interrupt globals in use?	bne,a,pn	%xcc, do_icpe_tl1_fatal	! Yep, irrecoverable	 wrpr		%g1, %tl		! Restore original trap level	add		%g2, 1, %g2		! Next trap level	cmp		%g2, %g1		! Hit them all yet?	ble,pt		%icc, 1b		! Not yet	 nop	wrpr		%g1, %tl		! Restore original trap leveldo_icpe_tl1_nonfatal:	/* Ok we may use interrupt globals safely. */	sethi		%hi(icache_parity_tl1_occurred), %g2	lduw		[%g2 + %lo(icache_parity_tl1_occurred)], %g1	add		%g1, 1, %g1	stw		%g1, [%g2 + %lo(icache_parity_tl1_occurred)]	/* Flush I-cache */	sethi		%hi(1 << 15), %g1	! I-cache size	mov		(1 << 5), %g2		! I-cache line size	sub		%g1, %g2, %g11:	or		%g1, (2 << 3), %g3	stxa		%g0, [%g3] ASI_IC_TAG	membar		#Sync	subcc		%g1, %g2, %g1	bge,pt		%icc, 1b	 nop	ba,pt		%xcc, dcpe_icpe_tl1_common	 nopdo_icpe_tl1_fatal:	sethi		%hi(1f), %g7	ba,pt		%xcc, etraptl11:	or		%g7, %lo(1b), %g7	mov		0x3, %o0	call		cheetah_plus_parity_error	 add		%sp, PTREGS_OFF, %o1	ba,pt		%xcc, rtrap	 clr		%l6	dcpe_icpe_tl1_common:	/* Flush D-cache, re-enable D/I caches in DCU and finally	 * retry the trapping instruction.	 */	sethi		%hi(1 << 16), %g1	! D-cache size	mov		(1 << 5), %g2		! D-cache line size	sub		%g1, %g2, %g11:	stxa		%g0, [%g1] ASI_DCACHE_TAG	membar		#Sync	subcc		%g1, %g2, %g1	bge,pt		%icc, 1b	 nop	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	or		%g1, (DCU_DC | DCU_IC), %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	retry	/* Capture I/D/E-cache state into per-cpu error scoreboard.	 *	 * %g1:		(TL>=0) ? 1 : 0	 * %g2:		scratch	 * %g3:		scratch	 * %g4:		AFSR	 * %g5:		AFAR	 * %g6:		current thread ptr	 * %g7:		scratch	 */__cheetah_log_error:	/* Put "TL1" software bit into AFSR. */	and		%g1, 0x1, %g1	sllx		%g1, 63, %g2	or		%g4, %g2, %g4	/* Get log entry pointer for this cpu at this trap level. */	BRANCH_IF_JALAPENO(g2,g3,50f)	ldxa		[%g0] ASI_SAFARI_CONFIG, %g2	srlx		%g2, 17, %g2	ba,pt		%xcc, 60f	 and		%g2, 0x3ff, %g250:	ldxa		[%g0] ASI_JBUS_CONFIG, %g2	srlx		%g2, 17, %g2	and		%g2, 0x1f, %g260:	sllx		%g2, 9, %g2	sethi		%hi(cheetah_error_log), %g3	ldx		[%g3 + %lo(cheetah_error_log)], %g3	brz,pn		%g3, 80f	 nop	add		%g3, %g2, %g3	sllx		%g1, 8, %g1	add		%g3, %g1, %g1	/* %g1 holds pointer to the top of the logging scoreboard */	ldx		[%g1 + 0x0], %g7	cmp		%g7, -1	bne,pn		%xcc, 80f	 nop	stx		%g4, [%g1 + 0x0]	stx		%g5, [%g1 + 0x8]	add		%g1, 0x10, %g1	/* %g1 now points to D-cache logging area */	set		0x3ff8, %g2	/* DC_addr mask		*/	and		%g5, %g2, %g2	/* DC_addr bits of AFAR	*/	srlx		%g5, 12, %g3	or		%g3, 1, %g3	/* PHYS tag + valid	*/10:	ldxa		[%g2] ASI_DCACHE_TAG, %g7	cmp		%g3, %g7	/* TAG match?		*/	bne,pt		%xcc, 13f	 nop	/* Yep, what we want, capture state. */	stx		%g2, [%g1 + 0x20]	stx		%g7, [%g1 + 0x28]	/* A membar Sync is required before and after utag access. */	membar		#Sync	ldxa		[%g2] ASI_DCACHE_UTAG, %g7	membar		#Sync	stx		%g7, [%g1 + 0x30]	ldxa		[%g2] ASI_DCACHE_SNOOP_TAG, %g7	stx		%g7, [%g1 + 0x38]	clr		%g312:	ldxa		[%g2 + %g3] ASI_DCACHE_DATA, %g7	stx		%g7, [%g1]	add		%g3, (1 << 5), %g3	cmp		%g3, (4 << 5)	bl,pt		%xcc, 12b	 add		%g1, 0x8, %g1	ba,pt		%xcc, 20f	 add		%g1, 0x20, %g113:	sethi		%hi(1 << 14), %g7	add		%g2, %g7, %g2	srlx		%g2, 14, %g7	cmp		%g7, 4	bl,pt		%xcc, 10b	 nop	add		%g1, 0x40, %g1	/* %g1 now points to I-cache logging area */20:	set		0x1fe0, %g2	/* IC_addr mask		*/	and		%g5, %g2, %g2	/* IC_addr bits of AFAR	*/	sllx		%g2, 1, %g2	/* IC_addr[13:6]==VA[12:5] */	srlx		%g5, (13 - 8), %g3 /* Make PTAG */	andn		%g3, 0xff, %g3	/* Mask off undefined bits */21:	ldxa		[%g2] ASI_IC_TAG, %g7	andn		%g7, 0xff, %g7	cmp		%g3, %g7	bne,pt		%xcc, 23f	 nop	/* Yep, what we want, capture state. */	stx		%g2, [%g1 + 0x40]	stx		%g7, [%g1 + 0x48]	add		%g2, (1 << 3), %g2	ldxa		[%g2] ASI_IC_TAG, %g7	add		%g2, (1 << 3), %g2	stx		%g7, [%g1 + 0x50]	ldxa		[%g2] ASI_IC_TAG, %g7	add		%g2, (1 << 3), %g2	stx		%g7, [%g1 + 0x60]	ldxa		[%g2] ASI_IC_TAG, %g7	stx		%g7, [%g1 + 0x68]	sub		%g2, (3 << 3), %g2	ldxa		[%g2] ASI_IC_STAG, %g7	stx		%g7, [%g1 + 0x58]	clr		%g3	srlx		%g2, 2, %g222:	ldxa		[%g2 + %g3] ASI_IC_INSTR, %g7	stx		%g7, [%g1]	add		%g3, (1 << 3), %g3	cmp		%g3, (8 << 3)	bl,pt		%xcc, 22b	 add		%g1, 0x8, %g1	ba,pt		%xcc, 30f	 add		%g1, 0x30, %g123:	sethi		%hi(1 << 14), %g7	add		%g2, %g7, %g2	srlx		%g2, 14, %g7	cmp		%g7, 4	bl,pt		%xcc, 21b	 nop	add		%g1, 0x70, %g1	/* %g1 now points to E-cache logging area */30:	andn		%g5, (32 - 1), %g2	stx		%g2, [%g1 + 0x20]	ldxa		[%g2] ASI_EC_TAG_DATA, %g7	stx		%g7, [%g1 + 0x28]	ldxa		[%g2] ASI_EC_R, %g0	clr		%g331:	ldxa		[%g3] ASI_EC_DATA, %g7	stx		%g7, [%g1 + %g3]