#define CEC1H_CR9       0x02#define CEC1H_CR8       0x01#define CEC2L_CR7       0x80#define CEC2L_CR6       0x40#define CEC2L_CR5       0x20#define CEC2L_CR4       0x10#define CEC2L_CR3       0x08#define CEC2L_CR2       0x04#define CEC2L_CR1       0x02#define CEC2L_CR0       0x01#define CEC2H_CR15      0x80#define CEC2H_CR14      0x40#define CEC2H_CR13      0x20#define CEC2H_CR12      0x10#define CEC2H_CR11      0x08#define CEC2H_CR10      0x04#define CEC2H_CR9       0x02#define CEC2H_CR8       0x01#define CEC3L_CR7       0x80#define CEC3L_CR6       0x40#define CEC3L_CR5       0x20#define CEC3L_CR4       0x10#define CEC3L_CR3       0x08#define CEC3L_CR2       0x04#define CEC3L_CR1       0x02#define CEC3L_CR0       0x01#define CEC3H_CR15      0x80#define CEC3H_CR14      0x40#define CEC3H_CR13      0x20#define CEC3H_CR12      0x10#define CEC3H_CR11      0x08#define CEC3H_CR10      0x04#define CEC3H_CR9       0x02#define CEC3H_CR8       0x01/* CECL (CRC Error Counter)   ------------------ T1 ----------------------------- */#define CECL_CR7        0x80#define CECL_CR6        0x40#define CECL_CR5        0x20#define CECL_CR4        0x10#define CECL_CR3        0x08#define CECL_CR2        0x04#define CECL_CR1        0x02#define CECL_CR0        0x01#define CECH_CR15       0x80#define CECH_CR14       0x40#define CECH_CR13       0x20#define CECH_CR12       0x10#define CECH_CR11       0x08#define CECH_CR10       0x04#define CECH_CR9        0x02#define CECH_CR8        0x01/* EBCL (E Bit Error Counter)   ------------------- E1 & T1 ------------------------- */#define EBCL_EB7        0x80#define EBCL_EB6        0x40#define EBCL_EB5        0x20#define EBCL_EB4        0x10#define EBCL_EB3        0x08#define EBCL_EB2        0x04#define EBCL_EB1        0x02#define EBCL_EB0        0x01#define EBCH_EB15       0x80#define EBCH_EB14       0x40#define EBCH_EB13       0x20#define EBCH_EB12       0x10#define EBCH_EB11       0x08#define EBCH_EB10       0x04#define EBCH_EB9        0x02#define EBCH_EB8        0x01/* RSA4-8 (Receive Sa4-8-Bit Register)   -------------------- E1 --------------------------- */#define RSA4_RS47       0x80#define RSA4_RS46       0x40#define RSA4_RS45       0x20#define RSA4_RS44       0x10#define RSA4_RS43       0x08#define RSA4_RS42       0x04#define RSA4_RS41       0x02#define RSA4_RS40       0x01#define RSA5_RS57       0x80#define RSA5_RS56       0x40#define RSA5_RS55       0x20#define RSA5_RS54       0x10#define RSA5_RS53       0x08#define RSA5_RS52       0x04#define RSA5_RS51       0x02#define RSA5_RS50       0x01#define RSA6_RS67       0x80#define RSA6_RS66       0x40#define RSA6_RS65       0x20#define RSA6_RS64       0x10#define RSA6_RS63       0x08#define RSA6_RS62       0x04#define RSA6_RS61       0x02#define RSA6_RS60       0x01#define RSA7_RS77       0x80#define RSA7_RS76       0x40#define RSA7_RS75       0x20#define RSA7_RS74       0x10#define RSA7_RS73       0x08#define RSA7_RS72       0x04#define RSA7_RS71       0x02#define RSA7_RS70       0x01#define RSA8_RS87       0x80#define RSA8_RS86       0x40#define RSA8_RS85       0x20#define RSA8_RS84       0x10#define RSA8_RS83       0x08#define RSA8_RS82       0x04#define RSA8_RS81       0x02#define RSA8_RS80       0x01/* RSA6S (Receive Sa6 Bit Status Register)   ------------------------ T1 ------------------------- */#define RSA6S_SX        0x20#define RSA6S_SF        0x10#define RSA6S_SE        0x08#define RSA6S_SC        0x04#define RSA6S_SA        0x02#define RSA6S_S8        0x01/* RDL1-3 Receive DL-Bit Register1-3)   ------------------------ T1 ------------------------- */#define RDL1_RDL17      0x80#define RDL1_RDL16      0x40#define RDL1_RDL15      0x20#define RDL1_RDL14      0x10#define RDL1_RDL13      0x08#define RDL1_RDL12      0x04#define RDL1_RDL11      0x02#define RDL1_RDL10      0x01#define RDL2_RDL27      0x80#define RDL2_RDL26      0x40#define RDL2_RDL25      0x20#define RDL2_RDL24      0x10#define RDL2_RDL23      0x08#define RDL2_RDL22      0x04#define RDL2_RDL21      0x02#define RDL2_RDL20      0x01#define RDL3_RDL37      0x80#define RDL3_RDL36      0x40#define RDL3_RDL35      0x20#define RDL3_RDL34      0x10#define RDL3_RDL33      0x08#define RDL3_RDL32      0x04#define RDL3_RDL31      0x02#define RDL3_RDL30      0x01/* SIS (Signaling Status Register)   -------------------- E1 & T1 -------------------------- */#define SIS_XDOV        0x80#define SIS_XFW         0x40#define SIS_XREP        0x20#define SIS_RLI         0x08#define SIS_CEC         0x04#define SIS_BOM         0x01/* RSIS (Receive Signaling Status Register)   -------------------- E1 & T1 --------------------------- */#define RSIS_VFR        0x80#define RSIS_RDO        0x40#define RSIS_CRC16      0x20#define RSIS_RAB        0x10#define RSIS_HA1        0x08#define RSIS_HA0        0x04#define RSIS_HFR        0x02#define RSIS_LA         0x01/* RBCL/H (Receive Byte Count Low/High)   ------------------- E1 & T1 ----------------------- */#define RBCL_RBC7       0x80#define RBCL_RBC6       0x40#define RBCL_RBC5       0x20#define RBCL_RBC4       0x10#define RBCL_RBC3       0x08#define RBCL_RBC2       0x04#define RBCL_RBC1       0x02#define RBCL_RBC0       0x01#define RBCH_OV         0x10#define RBCH_RBC11      0x08#define RBCH_RBC10      0x04#define RBCH_RBC9       0x02#define RBCH_RBC8       0x01/* ISR1-3  (Interrupt Status Register 1-3)   ------------------ E1 & T1 ------------------------------ */#define  FISR0_RME	0x80#define  FISR0_RFS	0x40#define  FISR0_T8MS	0x20#define  FISR0_ISF	0x20#define  FISR0_RMB	0x10#define  FISR0_CASC	0x08#define  FISR0_RSC	0x08#define  FISR0_CRC6	0x04#define  FISR0_CRC4	0x04#define  FISR0_PDEN	0x02#define  FISR0_RPF	0x01#define  FISR1_CASE	0x80#define  FISR1_LLBSC	0x80#define  FISR1_RDO	0x40#define  FISR1_ALLS	0x20#define  FISR1_XDU	0x10#define  FISR1_XMB	0x08#define  FISR1_XLSC	0x02#define  FISR1_XPR	0x01#define  FISR2_FAR	0x80#define  FISR2_LFA	0x40#define  FISR2_MFAR	0x20#define  FISR2_T400MS	0x10#define  FISR2_LMFA	0x10#define  FISR2_AIS	0x08#define  FISR2_LOS	0x04#define  FISR2_RAR	0x02#define  FISR2_RA	0x01#define  FISR3_ES	0x80#define  FISR3_SEC	0x40#define  FISR3_LMFA16	0x20#define  FISR3_AIS16	0x10#define  FISR3_RA16	0x08#define  FISR3_API	0x04#define  FISR3_XSLP	0x20#define  FISR3_XSLN	0x10#define  FISR3_LLBSC	0x08#define  FISR3_XRS	0x04#define  FISR3_SLN	0x02#define  FISR3_SLP	0x01/* GIS  (Global Interrupt Status Register)   --------------------- E1 & T1 --------------------- */#define  GIS_ISR3	0x08#define  GIS_ISR2	0x04#define  GIS_ISR1	0x02#define  GIS_ISR0	0x01/* VSTR  (Version Status Register)   --------------------- E1 & T1 --------------------- */#define  VSTR_VN3	0x08#define  VSTR_VN2	0x04#define  VSTR_VN1	0x02#define  VSTR_VN0	0x01/*>>>>>>>>>>>>>>>>>>>>>  Local Control Structures  <<<<<<<<<<<<<<<<<<<<<<<<< *//* Write-only Registers (E1/T1 control mode write registers) */#define XFIFOH	0x00		/* Tx FIFO High Byte */#define XFIFOL	0x01		/* Tx FIFO Low Byte */#define CMDR	0x02		/* Command Reg */#define DEC	0x60		/* Disable Error Counter */#define TEST2	0x62		/* Manuf. Test Reg 2 */#define XS(nbr)	(0x70 + (nbr))	/* Tx CAS Reg (0 to 15) *//* Read-write Registers (E1/T1 status mode read registers) */#define MODE	0x03	/* Mode Reg */#define RAH1	0x04	/* Receive Address High 1 */#define RAH2	0x05	/* Receive Address High 2 */#define RAL1	0x06	/* Receive Address Low 1 */#define RAL2	0x07	/* Receive Address Low 2 */#define IPC	0x08	/* Interrupt Port Configuration */#define CCR1	0x09	/* Common Configuration Reg 1 */#define CCR3	0x0A	/* Common Configuration Reg 3 */#define PRE	0x0B	/* Preamble Reg */#define RTR1	0x0C	/* Receive Timeslot Reg 1 */#define RTR2	0x0D	/* Receive Timeslot Reg 2 */#define RTR3	0x0E	/* Receive Timeslot Reg 3 */#define RTR4	0x0F	/* Receive Timeslot Reg 4 */#define TTR1	0x10	/* Transmit Timeslot Reg 1 */#define TTR2	0x11	/* Transmit Timeslot Reg 2 */#define TTR3	0x12	/* Transmit Timeslot Reg 3 */#define TTR4	0x13	/* Transmit Timeslot Reg 4 */#define IMR0	0x14	/* Interrupt Mask Reg 0 */#define IMR1	0x15	/* Interrupt Mask Reg 1 */#define IMR2	0x16	/* Interrupt Mask Reg 2 */#define IMR3	0x17	/* Interrupt Mask Reg 3 */#define IMR4	0x18	/* Interrupt Mask Reg 4 */#define IMR5	0x19	/* Interrupt Mask Reg 5 */#define FMR0	0x1A	/* Framer Mode Reigster 0 */#define FMR1	0x1B	/* Framer Mode Reigster 1 */#define FMR2	0x1C	/* Framer Mode Reigster 2 */#define LOOP	0x1D	/* Channel Loop Back */#define XSW	0x1E	/* Transmit Service Word */#define FMR4	0x1E	/* Framer Mode Reg 4 */#define XSP	0x1F	/* Transmit Spare Bits */#define FMR5	0x1F	/* Framer Mode Reg 5 */#define XC0	0x20	/* Transmit Control 0 */#define XC1	0x21	/* Transmit Control 1 */#define RC0	0x22	/* Receive Control 0 */#define RC1	0x23	/* Receive Control 1 */#define XPM0	0x24	/* Transmit Pulse Mask 0 */#define XPM1	0x25	/* Transmit Pulse Mask 1 */#define XPM2	0x26	/* Transmit Pulse Mask 2 */#define TSWM	0x27	/* Transparent Service Word Mask */#define TEST1	0x28	/* Manuf. Test Reg 1 */#define IDLE	0x29	/* Idle Channel Code */#define XSA4    0x2A	/* Transmit SA4 Bit Reg */#define XDL1	0x2A	/* Transmit DL-Bit Reg 2 */#define XSA5    0x2B	/* Transmit SA4 Bit Reg */#define XDL2	0x2B	/* Transmit DL-Bit Reg 2 */#define XSA6    0x2C	/* Transmit SA4 Bit Reg */#define XDL3	0x2C	/* Transmit DL-Bit Reg 2 */#define XSA7    0x2D	/* Transmit SA4 Bit Reg */#define CCB1	0x2D	/* Clear Channel Reg 1 */#define XSA8    0x2E	/* Transmit SA4 Bit Reg */#define CCB2	0x2E	/* Clear Channel Reg 2 */#define FMR3	0x2F	/* Framer Mode Reg. 3 */#define CCB3	0x2F	/* Clear Channel Reg 3 */#define ICB1	0x30	/* Idle Channel Reg 1 */#define ICB2	0x31	/* Idle Channel Reg 2 */#define ICB3	0x32	/* Idle Channel Reg 3 */#define ICB4	0x33	/* Idle Channel Reg 4 */#define LIM0	0x34	/* Line Interface Mode 0 */#define LIM1	0x35	/* Line Interface Mode 1 */#define PCDR	0x36	/* Pulse Count Detection */#define PCRR	0x37	/* Pulse Count Recovery */#define LIM2	0x38	/* Line Interface Mode Reg 2 */#define LCR1	0x39	/* Loop Code Reg 1 */#define LCR2	0x3A	/* Loop Code Reg 2 */#define LCR3	0x3B	/* Loop Code Reg 3 */#define SIC1	0x3C	/* System Interface Control 1 *//* Read-only Registers (E1/T1 control mode read registers) */#define RFIFOH	0x00		/* Receive FIFO */#define RFIFOL	0x01		/* Receive FIFO */#define FRS0	0x4C		/* Framer Receive Status 0 */#define FRS1	0x4D		/* Framer Receive Status 1 */#define RSW	0x4E		/* Receive Service Word */#define FRS2	0x4E		/* Framer Receive Status 2 */#define RSP	0x4F		/* Receive Spare Bits */#define FRS3	0x4F		/* Framer Receive Status 3 */#define FECL	0x50		/* Framing Error Counter */#define FECH	0x51		/* Framing Error Counter */#define CVCL	0x52		/* Code Violation Counter */#define CVCH	0x53		/* Code Violation Counter */#define CECL	0x54		/* CRC Error Counter 1 */#define CECH	0x55		/* CRC Error Counter 1 */#define EBCL	0x56		/* E-Bit Error Counter */#define EBCH	0x57		/* E-Bit Error Counter */#define BECL	0x58		/* Bit Error Counter Low */#define BECH	0x59		/* Bit Error Counter Low */#define CEC3	0x5A		/* CRC Error Counter 3 (16-bit) */#define RSA4	0x5C		/* Receive SA4 Bit Reg */#define RDL1	0x5C		/* Receive DL-Bit Reg 1 */#define RSA5	0x5D		/* Receive SA5 Bit Reg */#define RDL2	0x5D		/* Receive DL-Bit Reg 2 */#define RSA6	0x5E		/* Receive SA6 Bit Reg */#define RDL3	0x5E		/* Receive DL-Bit Reg 3 */#define RSA7	0x5F		/* Receive SA7 Bit Reg */#define RSA8	0x60		/* Receive SA8 Bit Reg */#define RSA6S	0x61		/* Receive SA6 Bit Status Reg */#define TSR0	0x62		/* Manuf. Test Reg 0 */#define TSR1	0x63		/* Manuf. Test Reg 1 */#define SIS	0x64		/* Signaling Status Reg */#define RSIS	0x65		/* Receive Signaling Status Reg */#define RBCL	0x66		/* Receive Byte Control */#define RBCH	0x67		/* Receive Byte Control */#define FISR0	0x68		/* Interrupt Status Reg 0 */#define FISR1	0x69		/* Interrupt Status Reg 1 */#define FISR2	0x6A		/* Interrupt Status Reg 2 */#define FISR3	0x6B		/* Interrupt Status Reg 3 */#define GIS	0x6E		/* Global Interrupt Status */#define VSTR	0x6F		/* Version Status */#define RS(nbr)	(0x70 + (nbr))	/* Rx CAS Reg (0 to 15) */#endif	/* _FALC_LH_H */