#ifndef XTENSA_HAL_H#define XTENSA_HAL_H/* * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND * * include/asm-xtensa/xtensa/hal.h -- contains a definition of the * Core HAL interface. * * All definitions in this header file are independent of any specific * Xtensa processor configuration.  Thus an OS or other software can * include this header file and be compiled into configuration- * independent objects that can be distributed and eventually linked * to the HAL library (libhal.a) to create a configuration-specific * final executable. * * Certain definitions, however, are release-specific -- such as the * XTHAL_RELEASE_xxx macros (or additions made in later releases). * * This file is subject to the terms and conditions of the GNU General Public * License.  See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2002 Tensilica Inc. *//*----------------------------------------------------------------------  			 Constant Definitions			(shared with assembly)  ----------------------------------------------------------------------*//*  Software release information (not configuration-specific!):  */#define XTHAL_RELEASE_MAJOR	1050#define XTHAL_RELEASE_MINOR	0#define XTHAL_RELEASE_NAME	"T1050.0-2002-08-06-eng0"#define XTHAL_RELEASE_INTERNAL	"2002-08-06-eng0"#define XTHAL_REL_T1050	1#define XTHAL_REL_T1050_0	1#define XTHAL_REL_T1050_0_2002	1#define XTHAL_REL_T1050_0_2002_08	1#define XTHAL_REL_T1050_0_2002_08_06	1#define XTHAL_REL_T1050_0_2002_08_06_ENG0	1/*  HAL version numbers (these names are for backward compatibility):  */#define XTHAL_MAJOR_REV		XTHAL_RELEASE_MAJOR#define XTHAL_MINOR_REV		XTHAL_RELEASE_MINOR/* *  A bit of software release history on values of XTHAL_{MAJOR,MINOR}_REV: * *	Release		MAJOR	MINOR		Comment *	=======		=====	=====		======= *	T1015.n		n/a	n/a		(HAL not yet available) *	T1020.{0,1,2}	0	1		(HAL beta) *	T1020.{3,4}	0	2		First release. *	T1020.n (n>4)	0	2 or >3		(TBD) *	T1030.0		0	1		(HAL beta) *	T1030.{1,2}	0	3		Equivalent to first release. *	T1030.n (n>=3)	0	>= 3		(TBD) *	T1040.n		1040	n		Full CHAL available from T1040.2 *	T1050.n		1050	n		Current release. * * *  Note:  there is a distinction between the software release with *  which something is compiled (accessible using XTHAL_RELEASE_* macros) *  and the software release with which the HAL library was compiled *  (accessible using Xthal_release_* global variables).  This *  distinction is particularly relevant for vendors that distribute *  configuration-independent binaries (eg. an OS), where their customer *  might link it with a HAL of a different Xtensa software release. *  In this case, it may be appropriate for the OS to verify at run-time *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible. *  [Guidelines as to which release is compatible with which are not *  currently provided explicitly, but might be inferred from reading *  OSKit documentation for all releases -- compatibility is also highly *  dependent on which HAL features are used.  Each release is usually *  backward compatible, with very few exceptions if any.] * *  Notes: *	Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only. *	Tornado 2.0.2 supported in T1040.2+, and T1050. *	Compile-time HAL port of NucleusPlus supported by T1040.2+ and T1050. *//* *  Architectural limits, independent of configuration. *  Note that these are ISA-defined limits, not micro-architecture implementation *  limits enforced by the Xtensa Processor Generator (which may be stricter than *  these below). */#define XTHAL_MAX_CPS		8	/* max number of coprocessors (0..7) */#define XTHAL_MAX_INTERRUPTS	32	/* max number of interrupts (0..31) */#define XTHAL_MAX_INTLEVELS	16	/* max number of interrupt levels (0..15) */					/* (as of T1040, implementation limit is 7: 0..6) */#define XTHAL_MAX_TIMERS	4	/* max number of timers (CCOMPARE0..CCOMPARE3) */					/* (as of T1040, implementation limit is 3: 0..2) *//*  Misc:  */#define XTHAL_LITTLEENDIAN		0#define XTHAL_BIGENDIAN			1/*  Interrupt types:  */#define XTHAL_INTTYPE_UNCONFIGURED	0#define XTHAL_INTTYPE_SOFTWARE		1#define XTHAL_INTTYPE_EXTERN_EDGE	2#define XTHAL_INTTYPE_EXTERN_LEVEL	3#define XTHAL_INTTYPE_TIMER		4#define XTHAL_INTTYPE_NMI		5#define XTHAL_MAX_INTTYPES		6	/* number of interrupt types *//*  Timer related:  */#define XTHAL_TIMER_UNCONFIGURED	-1	/* Xthal_timer_interrupt[] value for non-existent timers */#define XTHAL_TIMER_UNASSIGNED	XTHAL_TIMER_UNCONFIGURED	/* (for backwards compatibility only) *//*  Access Mode bits (tentative):  */	/* bit abbr unit short_name       PPC equ - Description */#define XTHAL_AMB_EXCEPTION	0	/* 001 E EX fls: EXception        none    - generate exception on any access (aka "illegal") */#define XTHAL_AMB_HITCACHE	1	/* 002 C CH fls: use Cache on Hit ~(I CI) - use cache on hit -- way from tag match [or H HC, or U UC] (ISA: same, except for Isolate case) */#define XTHAL_AMB_ALLOCATE	2	/* 004 A AL fl?: ALlocate         none    - refill cache on miss -- way from LRU [or F FI fill] (ISA: Read/Write Miss Refill) */#define XTHAL_AMB_WRITETHRU	3	/* 008 W WT --s: WriteThrough     W WT    - store immediately to memory (ISA: same) */#define XTHAL_AMB_ISOLATE	4	/* 010 I IS fls: ISolate          none    - use cache regardless of hit-vs-miss -- way from vaddr (ISA: use-cache-on-miss+hit) */#define XTHAL_AMB_GUARD		5	/* 020 G GU ?l?: GUard            G *     - non-speculative; spec/replay refs not permitted */#if 0#define XTHAL_AMB_ORDERED	x	/* 000 O OR fls: ORdered          G *     - mem accesses cannot be out of order */#define XTHAL_AMB_FUSEWRITES	x	/* 000 F FW --s: FuseWrites       none    - allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */#define XTHAL_AMB_COHERENT	x	/* 000 M MC fl?: Mem/MP Coherent  M       - on reads, other CPUs/bus-masters may need to supply data */#define XTHAL_AMB_TRUSTED	x	/* 000 T TR ?l?: TRusted          none    - memory will not bus error (if it does, handle as fatal imprecise interrupt) */#define XTHAL_AMB_PREFETCH	x	/* 000 P PR fl?: PRefetch         none    - on refill, read line+1 into prefetch buffers */#define XTHAL_AMB_STREAM	x	/* 000 S ST ???: STreaming        none    - access one of N stream buffers */#endif /*0*/#define XTHAL_AM_EXCEPTION	(1<<XTHAL_AMB_EXCEPTION)#define XTHAL_AM_HITCACHE	(1<<XTHAL_AMB_HITCACHE)#define XTHAL_AM_ALLOCATE	(1<<XTHAL_AMB_ALLOCATE)#define XTHAL_AM_WRITETHRU	(1<<XTHAL_AMB_WRITETHRU)#define XTHAL_AM_ISOLATE	(1<<XTHAL_AMB_ISOLATE)#define XTHAL_AM_GUARD		(1<<XTHAL_AMB_GUARD)#if 0#define XTHAL_AM_ORDERED	(1<<XTHAL_AMB_ORDERED)#define XTHAL_AM_FUSEWRITES	(1<<XTHAL_AMB_FUSEWRITES)#define XTHAL_AM_COHERENT	(1<<XTHAL_AMB_COHERENT)#define XTHAL_AM_TRUSTED	(1<<XTHAL_AMB_TRUSTED)#define XTHAL_AM_PREFETCH	(1<<XTHAL_AMB_PREFETCH)#define XTHAL_AM_STREAM		(1<<XTHAL_AMB_STREAM)#endif /*0*//* *  Allowed Access Modes (bit combinations). * *  Columns are: *  "FOGIWACE" *	Access mode bits (see XTHAL_AMB_xxx above). *	<letter> = bit is set *	'-'      = bit is clear *	'.'      = bit is irrelevant / don't care, as follows: *			E=1 makes all others irrelevant *			W,F relevant only for stores *  "2345" *	Indicates which Xtensa releases support the corresponding *	access mode.  Releases for each character column are: *		2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1 *		3 = T1020.2 and later:  T1020.2+, T1030 *		4 = T1040 *		5 = T1050 (maybe) *	And the character column contents are: *		<number> = support by release(s) *		"." = unsupported by release(s) *		"?" = support unknown */					/* FOGIWACE 2345 *//*  For instruction fetch:  */#define XTHAL_FAM_EXCEPTION	0x001	/* .......E 2345 exception */#define XTHAL_FAM_ISOLATE	0x012	/* .--I.-C- .... isolate */#define XTHAL_FAM_BYPASS	0x000	/* .---.--- 2345 bypass */#define XTHAL_FAM_NACACHED	0x002	/* .---.-C- .... cached no-allocate (frozen) */#define XTHAL_FAM_CACHED	0x006	/* .---.AC- 2345 cached *//*  For data load:  */#define XTHAL_LAM_EXCEPTION	0x001	/* .......E 2345 exception */#define XTHAL_LAM_ISOLATE	0x012	/* .--I.-C- 2345 isolate */#define XTHAL_LAM_BYPASS	0x000	/* .O--.--- 2... bypass speculative */#define XTHAL_LAM_BYPASSG	0x020	/* .OG-.--- .345 bypass guarded */#define XTHAL_LAM_NACACHED	0x002	/* .O--.-C- 2... cached no-allocate speculative */#define XTHAL_LAM_NACACHEDG	0x022	/* .OG-.-C- .345 cached no-allocate guarded */#define XTHAL_LAM_CACHED	0x006	/* .---.AC- 2345 cached speculative */#define XTHAL_LAM_CACHEDG	0x026	/* .?G-.AC- .... cached guarded *//*  For data store:  */#define XTHAL_SAM_EXCEPTION	0x001	/* .......E 2345 exception */#define XTHAL_SAM_ISOLATE	0x032	/* .-GI--C- 2345 isolate */#define XTHAL_SAM_BYPASS	0x028	/* -OG-W--- 2345 bypass *//*efine XTHAL_SAM_BYPASSF	0x028*/	/* F-G-W--- ...? bypass write-combined */#define XTHAL_SAM_WRITETHRU	0x02A	/* -OG-W-C- 234? writethrough *//*efine XTHAL_SAM_WRITETHRUF	0x02A*/	/* F-G-W-C- ...5 writethrough write-combined */#define XTHAL_SAM_WRITEALLOC	0x02E	/* -OG-WAC- ...? writethrough-allocate *//*efine XTHAL_SAM_WRITEALLOCF	0x02E*/	/* F-G-WAC- ...? writethrough-allocate write-combined */#define XTHAL_SAM_WRITEBACK	0x026	/* F-G--AC- ...5 writeback */#if 0/*    Cache attribute encoding for CACHEATTR (per ISA):    (Note:  if this differs from ISA Ref Manual, ISA has precedence)	Inst-fetches	Loads		Stores	-------------	------------	-------------0x0	FCA_EXCEPTION  ?LCA_NACACHED_G*	SCA_WRITETHRU	"uncached"0x1	FCA_CACHED	LCA_CACHED	SCA_WRITETHRU	cached0x2	FCA_BYPASS	LCA_BYPASS_G*	SCA_BYPASS	bypass0x3	FCA_CACHED	LCA_CACHED	SCA_WRITEALLOCF	write-allocate		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)0x4	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK	write-back		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)0x5..D	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(reserved)0xE	FCA_EXCEPTION	LCA_ISOLATE	SCA_ISOLATE	isolate0xF	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	illegal     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)*/#endif /*0*/#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)#ifdef __cplusplusextern "C" {#endif/*----------------------------------------------------------------------  			     HAL  ----------------------------------------------------------------------*//* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */extern const unsigned int Xthal_rev_no;/*----------------------------------------------------------------------  			Processor State  ----------------------------------------------------------------------*//* save & restore the extra processor state */extern void xthal_save_extra(void *base);extern void xthal_restore_extra(void *base);extern void xthal_save_cpregs(void *base, int);extern void xthal_restore_cpregs(void *base, int);/*extern void xthal_save_all_extra(void *base);*//*extern void xthal_restore_all_extra(void *base);*//* space for processor state */extern const unsigned int Xthal_extra_size;extern const unsigned int Xthal_extra_align;/* space for TIE register files */extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];/* total of space for the processor state (for Tor2) */extern const unsigned int Xthal_all_extra_size;extern const unsigned int Xthal_all_extra_align;/* initialize the extra processor *//*extern void xthal_init_extra(void);*//* initialize the TIE coprocessor *//*extern void xthal_init_cp(int);*//* initialize the extra processor */extern void xthal_init_mem_extra(void *);/* initialize the TIE coprocessor */extern void xthal_init_mem_cp(void *, int);/* validate & invalidate the TIE register file */extern void xthal_validate_cp(int);extern void xthal_invalidate_cp(int);/* the number of TIE coprocessors contiguous from zero (for Tor2) */extern const unsigned int Xthal_num_coprocessors;/* actual number of coprocessors */