?? maichong.rpt
字號:
- 6 - A 08 OR2 s 0 4 0 1 ~167~1
- 7 - A 09 OR2 s 0 4 0 1 ~167~2
- 8 - A 09 OR2 s 0 4 0 1 ~167~3
- 8 - A 07 AND2 1 1 1 8 :274
- 4 - A 17 AND2 s ! 0 3 0 2 ~702~1
- 7 - A 17 OR2 ! 0 4 0 2 :742
- 5 - A 20 AND2 0 4 0 2 :762
- 5 - A 14 AND2 s 0 2 0 10 ~822~1
- 6 - B 24 AND2 s 0 4 0 2 ~842~1
- 3 - A 14 AND2 0 4 1 1 :842
- 6 - A 20 AND2 s ! 0 3 0 4 ~862~1
- 4 - A 20 AND2 s 0 3 0 3 ~882~1
- 3 - A 20 OR2 0 3 1 0 :885
- 1 - A 20 OR2 ! 0 3 0 1 :908
- 6 - A 14 OR2 0 4 1 0 :918
- 8 - A 14 OR2 0 4 1 0 :984
- 1 - A 17 OR2 0 4 0 1 :1001
- 7 - A 20 OR2 0 4 0 1 :1011
- 4 - A 14 OR2 s 0 4 0 1 ~1013~1
- 2 - A 20 OR2 0 4 1 0 :1017
- 7 - A 14 OR2 0 4 1 0 :1050
- 8 - A 17 AND2 s 0 3 0 1 ~1077~1
- 6 - A 17 AND2 s 0 2 0 1 ~1085~1
- 2 - A 17 OR2 s 0 4 0 1 ~1085~2
- 8 - A 20 OR2 0 4 1 0 :1085
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\isp\maichong\maichong.rpt
maichong
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 9/ 48( 18%) 11/ 48( 22%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 2/ 96( 2%) 1/ 48( 2%) 4/ 48( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\isp\maichong\maichong.rpt
maichong
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
LCELL 9 :274
Device-Specific Information: d:\isp\maichong\maichong.rpt
maichong
** EQUATIONS **
clk : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
load : INPUT;
-- Node name is ':38' = 'control'
-- Equation name is 'control', location is LC5_A7, type is buried.
control = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, !_LC3_A7);
_EQ001 = _LC6_A8
# _LC8_A9
# _LC1_A7;
-- Node name is ':76' = 'count0~182'
-- Equation name is 'count0~182', location is LC4_A8, type is buried.
count0~182 = DFFE( _EQ002, GLOBAL( clk), !(GLOBAL( load) & !D0), !(GLOBAL( load) & D0), VCC);
_EQ002 = count0~182 & _LC1_A8 & !_LC2_A8
# !count0~182 & !_LC1_A8 & !_LC2_A8;
-- Node name is ':77' = 'count1~182'
-- Equation name is 'count1~182', location is LC7_A8, type is buried.
count1~182 = DFFE( _EQ003, GLOBAL( clk), !(GLOBAL( load) & !D1), !(GLOBAL( load) & D1), VCC);
_EQ003 = count1~182 & !_LC2_A8 & _LC5_A8
# !count1~182 & !_LC2_A8 & !_LC5_A8;
-- Node name is ':78' = 'count2~182'
-- Equation name is 'count2~182', location is LC3_A8, type is buried.
count2~182 = DFFE( _EQ004, GLOBAL( clk), !(GLOBAL( load) & !D2), !(GLOBAL( load) & D2), VCC);
_EQ004 = count2~182 & !_LC2_A8 & _LC6_A7
# !count2~182 & !_LC2_A8 & !_LC6_A7;
-- Node name is ':79' = 'count3~182'
-- Equation name is 'count3~182', location is LC2_A7, type is buried.
count3~182 = DFFE( _LC1_A7, GLOBAL( clk), !(GLOBAL( load) & !D3), !(GLOBAL( load) & D3), VCC);
-- Node name is ':80' = 'count4~182'
-- Equation name is 'count4~182', location is LC3_A9, type is buried.
count4~182 = DFFE( _EQ005, GLOBAL( clk), !(GLOBAL( load) & !D4), !(GLOBAL( load) & D4), VCC);
_EQ005 = count4~182 & !_LC2_A8 & _LC4_A9
# !count4~182 & !_LC2_A8 & !_LC4_A9;
-- Node name is ':81' = 'count5~182'
-- Equation name is 'count5~182', location is LC2_A9, type is buried.
count5~182 = DFFE( _EQ006, GLOBAL( clk), !(GLOBAL( load) & !D5), !(GLOBAL( load) & D5), VCC);
_EQ006 = count5~182 & _LC1_A9 & !_LC2_A8
# !count5~182 & !_LC1_A9 & !_LC2_A8;
-- Node name is ':82' = 'count6~182'
-- Equation name is 'count6~182', location is LC5_A9, type is buried.
count6~182 = DFFE( _EQ007, GLOBAL( clk), !(GLOBAL( load) & !D6), !(GLOBAL( load) & D6), VCC);
_EQ007 = count6~182 & count7~182 & !_LC2_A8
# !count6~182 & !count7~182 & !_LC2_A8;
-- Node name is ':83' = 'count7~182'
-- Equation name is 'count7~182', location is LC6_A9, type is buried.
count7~182 = DFFE( _EQ008, GLOBAL( clk), !(GLOBAL( load) & !D7), !(GLOBAL( load) & D7), VCC);
_EQ008 = !count7~182 & !_LC2_A8;
-- Node name is 'dis0'
-- Equation name is 'dis0', type is output
dis0 = pcount0;
-- Node name is 'dis1'
-- Equation name is 'dis1', type is output
dis1 = pcount1;
-- Node name is 'dis2'
-- Equation name is 'dis2', type is output
dis2 = pcount2;
-- Node name is 'dis3'
-- Equation name is 'dis3', type is output
dis3 = pcount3;
-- Node name is 'dis4'
-- Equation name is 'dis4', type is output
dis4 = pcount4;
-- Node name is 'dis5'
-- Equation name is 'dis5', type is output
dis5 = pcount5;
-- Node name is 'dis6'
-- Equation name is 'dis6', type is output
dis6 = pcount6;
-- Node name is 'dis7'
-- Equation name is 'dis7', type is output
dis7 = pcount7;
-- Node name is 'lcdcontrol0'
-- Equation name is 'lcdcontrol0', type is output
lcdcontrol0 = GND;
-- Node name is 'lcdcontrol1'
-- Equation name is 'lcdcontrol1', type is output
lcdcontrol1 = GND;
-- Node name is 'lcdcontrol2'
-- Equation name is 'lcdcontrol2', type is output
lcdcontrol2 = GND;
-- Node name is 'lcdcontrol3'
-- Equation name is 'lcdcontrol3', type is output
lcdcontrol3 = GND;
-- Node name is 'lcdcontrol4'
-- Equation name is 'lcdcontrol4', type is output
lcdcontrol4 = GND;
-- Node name is 'lcdcontrol5'
-- Equation name is 'lcdcontrol5', type is output
lcdcontrol5 = GND;
-- Node name is 'lcdcontrol6'
-- Equation name is 'lcdcontrol6', type is output
lcdcontrol6 = GND;
-- Node name is 'lcdcontrol7'
-- Equation name is 'lcdcontrol7', type is output
lcdcontrol7 = VCC;
-- Node name is 'lcd0'
-- Equation name is 'lcd0', type is output
lcd0 = _LC3_A20;
-- Node name is 'lcd1'
-- Equation name is 'lcd1', type is output
lcd1 = _LC6_A14;
-- Node name is 'lcd2'
-- Equation name is 'lcd2', type is output
lcd2 = !_LC3_A14;
-- Node name is 'lcd3'
-- Equation name is 'lcd3', type is output
lcd3 = _LC8_A14;
-- Node name is 'lcd4'
-- Equation name is 'lcd4', type is output
lcd4 = _LC2_A20;
-- Node name is 'lcd5'
-- Equation name is 'lcd5', type is output
lcd5 = _LC7_A14;
-- Node name is 'lcd6'
-- Equation name is 'lcd6', type is output
lcd6 = _LC8_A20;
-- Node name is 'lcd7'
-- Equation name is 'lcd7', type is output
lcd7 = GND;
-- Node name is 'load~1'
-- Equation name is 'load~1', location is LC3_A7, type is buried.
-- synthesized logic cell
!_LC3_A7 = _LC3_A7~NOT;
_LC3_A7~NOT = LCELL(!load);
-- Node name is ':39' = 'pcount0'
-- Equation name is 'pcount0', location is LC7_B24, type is buried.
pcount0 = DFFE( _EQ009, _LC8_A7, VCC, VCC, VCC);
_EQ009 = pcount0 & !pcount2
# !_LC4_B24 & pcount0
# pcount0 & !pcount1
# _LC4_B24 & !pcount0 & pcount1 & pcount2;
-- Node name is ':40' = 'pcount1'
-- Equation name is 'pcount1', location is LC1_B24, type is buried.
pcount1 = DFFE( _EQ010, _LC8_A7, VCC, VCC, VCC);
_EQ010 = pcount1 & !pcount2
# !_LC4_B24 & pcount1
# _LC4_B24 & !pcount1 & pcount2;
-- Node name is ':41' = 'pcount2'
-- Equation name is 'pcount2', location is LC5_B24, type is buried.
pcount2 = DFFE( _EQ011, _LC8_A7, VCC, VCC, VCC);
_EQ011 = !_LC4_B24 & pcount2
# _LC4_B24 & !pcount2;
-- Node name is ':42' = 'pcount3'
-- Equation name is 'pcount3', location is LC3_B24, type is buried.
pcount3 = DFFE( _EQ012, _LC8_A7, VCC, VCC, VCC);
_EQ012 = pcount3 & !pcount4
# !_LC1_A14 & pcount3
# _LC1_A14 & !pcount3 & pcount4;
-- Node name is ':43' = 'pcount4'
-- Equation name is 'pcount4', location is LC2_B24, type is buried.
pcount4 = DFFE( _EQ013, _LC8_A7, VCC, VCC, VCC);
_EQ013 = !_LC1_A14 & pcount4
# _LC1_A14 & !pcount4;
-- Node name is ':44' = 'pcount5'
-- Equation name is 'pcount5', location is LC5_A17, type is buried.
pcount5 = DFFE( _EQ014, _LC8_A7, VCC, VCC, VCC);
_EQ014 = pcount5 & !pcount6
# pcount5 & !pcount7
# !pcount5 & pcount6 & pcount7;
-- Node name is ':45' = 'pcount6'
-- Equation name is 'pcount6', location is LC3_A17, type is buried.
pcount6 = DFFE( _EQ015, _LC8_A7, VCC, VCC, VCC);
_EQ015 = pcount6 & !pcount7
# !pcount6 & pcount7;
-- Node name is ':46' = 'pcount7'
-- Equation name is 'pcount7', location is LC2_A14, type is buried.
pcount7 = DFFE(!pcount7, _LC8_A7, VCC, VCC, VCC);
-- Node name is 'pout'
-- Equation name is 'pout', type is output
pout = _LC8_A7;
-- Node name is 'test'
-- Equation name is 'test', type is output
test = control;
-- Node name is '|LPM_ADD_SUB:112|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ016);
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