_EQ016 =  count7~182
         #  count6~182;

-- Node name is '|LPM_ADD_SUB:112|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A9', type is buried 
_LC4_A9  = LCELL( _EQ017);
  _EQ017 =  count5~182
         #  _LC1_A9;

-- Node name is '|LPM_ADD_SUB:112|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A7', type is buried 
_LC6_A7  = LCELL( _EQ018);
  _EQ018 =  count3~182
         #  count4~182
         #  _LC4_A9;

-- Node name is '|LPM_ADD_SUB:112|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = LCELL( _EQ019);
  _EQ019 =  count2~182
         #  _LC6_A7;

-- Node name is '|LPM_ADD_SUB:112|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ020);
  _EQ020 =  count1~182
         #  count2~182
         #  _LC6_A7;

-- Node name is '|LPM_ADD_SUB:302|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ021);
  _EQ021 =  pcount5 &  pcount6 &  pcount7;

-- Node name is '|LPM_ADD_SUB:302|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = LCELL( _EQ022);
  _EQ022 =  _LC1_A14 &  pcount3 &  pcount4;

-- Node name is ':94' 
-- Equation name is '_LC2_A8', type is buried 
!_LC2_A8 = _LC2_A8~NOT;
_LC2_A8~NOT = LCELL( _EQ023);
  _EQ023 =  count0~182
         #  _LC1_A8;

-- Node name is ':141' 
-- Equation name is '_LC1_A7', type is buried 
_LC1_A7  = LCELL( _EQ024);
  _EQ024 =  count3~182 &  count4~182 & !_LC2_A8
         #  count3~182 & !_LC2_A8 &  _LC4_A9
         # !count3~182 & !count4~182 & !_LC2_A8 & !_LC4_A9;

-- Node name is '~167~1' 
-- Equation name is '~167~1', location is LC6_A8, type is buried.
-- synthesized logic cell 
_LC6_A8  = LCELL( _EQ025);
  _EQ025 =  count2~182 &  _LC6_A7
         #  count0~182
         #  count1~182;

-- Node name is '~167~2' 
-- Equation name is '~167~2', location is LC7_A9, type is buried.
-- synthesized logic cell 
_LC7_A9  = LCELL( _EQ026);
  _EQ026 =  count5~182 &  _LC1_A9 & !_LC2_A8
         # !count5~182 & !_LC1_A9 & !_LC2_A8
         #  count4~182 &  count5~182 & !_LC2_A8
         #  count4~182 &  _LC1_A9 & !_LC2_A8;

-- Node name is '~167~3' 
-- Equation name is '~167~3', location is LC8_A9, type is buried.
-- synthesized logic cell 
_LC8_A9  = LCELL( _EQ027);
  _EQ027 =  _LC7_A9
         #  count6~182 & !_LC2_A8
         # !count7~182 & !_LC2_A8;

-- Node name is ':274' 
-- Equation name is '_LC8_A7', type is buried 
_LC8_A7  = LCELL( _EQ028);
  _EQ028 =  clk &  control;

-- Node name is '~702~1' 
-- Equation name is '~702~1', location is LC4_A17, type is buried.
-- synthesized logic cell 
!_LC4_A17 = _LC4_A17~NOT;
_LC4_A17~NOT = LCELL( _EQ029);
  _EQ029 =  _LC6_B24 &  pcount4 & !pcount5;

-- Node name is ':742' 
-- Equation name is '_LC7_A17', type is buried 
!_LC7_A17 = _LC7_A17~NOT;
_LC7_A17~NOT = LCELL( _EQ030);
  _EQ030 = !pcount6
         # !pcount7
         # !pcount5
         # !_LC5_A14;

-- Node name is ':762' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ031);
  _EQ031 =  _LC5_A14 &  pcount5 &  pcount6 & !pcount7;

-- Node name is '~822~1' 
-- Equation name is '~822~1', location is LC5_A14, type is buried.
-- synthesized logic cell 
_LC5_A14 = LCELL( _EQ032);
  _EQ032 =  _LC6_B24 & !pcount4;

-- Node name is '~842~1' 
-- Equation name is '~842~1', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ033);
  _EQ033 = !pcount0 & !pcount1 & !pcount2 & !pcount3;

-- Node name is ':842' 
-- Equation name is '_LC3_A14', type is buried 
_LC3_A14 = LCELL( _EQ034);
  _EQ034 =  _LC5_A14 & !pcount5 &  pcount6 & !pcount7;

-- Node name is '~862~1' 
-- Equation name is '~862~1', location is LC6_A20, type is buried.
-- synthesized logic cell 
!_LC6_A20 = _LC6_A20~NOT;
_LC6_A20~NOT = LCELL( _EQ035);
  _EQ035 =  _LC5_A14 & !pcount6 &  pcount7;

-- Node name is '~882~1' 
-- Equation name is '~882~1', location is LC4_A20, type is buried.
-- synthesized logic cell 
_LC4_A20 = LCELL( _EQ036);
  _EQ036 =  _LC5_A14 & !pcount6 & !pcount7;

-- Node name is ':885' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ037);
  _EQ037 = !_LC4_A20 &  _LC6_A20
         # !_LC4_A20 &  pcount5
         #  _LC6_A20 & !pcount5
         #  _LC4_A20 & !pcount5;

-- Node name is ':908' 
-- Equation name is '_LC1_A20', type is buried 
!_LC1_A20 = _LC1_A20~NOT;
_LC1_A20~NOT = LCELL( _EQ038);
  _EQ038 =  _LC5_A20
         # !_LC6_A20 &  pcount5;

-- Node name is ':918' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ039);
  _EQ039 = !_LC5_A14
         # !pcount5
         #  pcount6 &  pcount7
         # !pcount6 & !pcount7;

-- Node name is ':984' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ040);
  _EQ040 = !_LC5_A14
         #  pcount6 & !pcount7
         # !pcount5 &  pcount6
         # !pcount5 & !pcount7
         #  pcount5 & !pcount6 &  pcount7;

-- Node name is ':1001' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ041);
  _EQ041 = !_LC7_A17 &  pcount6
         # !_LC7_A17 & !pcount7
         #  _LC4_A17 & !_LC7_A17;

-- Node name is ':1011' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ042);
  _EQ042 =  _LC3_A14
         #  _LC1_A17 &  _LC4_A14
         #  _LC4_A14 &  _LC5_A20;

-- Node name is '~1013~1' 
-- Equation name is '~1013~1', location is LC4_A14, type is buried.
-- synthesized logic cell 
_LC4_A14 = LCELL( _EQ043);
  _EQ043 = !_LC5_A14
         #  pcount6 & !pcount7
         #  pcount5 &  pcount6
         # !pcount5 & !pcount6
         # !pcount5 & !pcount7;

-- Node name is ':1017' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ044);
  _EQ044 =  _LC4_A20 & !pcount5
         #  _LC6_A20 &  _LC7_A20
         #  _LC7_A20 &  pcount5;

-- Node name is ':1050' 
-- Equation name is '_LC7_A14', type is buried 
_LC7_A14 = LCELL( _EQ045);
  _EQ045 = !_LC5_A14
         # !pcount6 & !pcount7
         #  pcount5 & !pcount6
         #  pcount5 & !pcount7;

-- Node name is '~1077~1' 
-- Equation name is '~1077~1', location is LC8_A17, type is buried.
-- synthesized logic cell 
_LC8_A17 = LCELL( _EQ046);
  _EQ046 =  _LC5_A14 & !pcount5 &  pcount6;

-- Node name is '~1085~1' 
-- Equation name is '~1085~1', location is LC6_A17, type is buried.
-- synthesized logic cell 
_LC6_A17 = LCELL( _EQ047);
  _EQ047 = !_LC4_A17 & !pcount6;

-- Node name is '~1085~2' 
-- Equation name is '~1085~2', location is LC2_A17, type is buried.
-- synthesized logic cell 
_LC2_A17 = LCELL( _EQ048);
  _EQ048 =  _LC6_A17 & !_LC7_A17
         # !_LC1_A20
         #  _LC8_A17;

-- Node name is ':1085' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ049);
  _EQ049 =  _LC4_A20 &  pcount5
         #  _LC2_A17 &  pcount5
         #  _LC2_A17 & !_LC4_A20 &  _LC6_A20;



Project Information                               d:\isp\maichong\maichong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,391K