library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity maichong is  
   port (D:in std_logic_vector(0 to 7); 
			load:in std_logic;
         clk:in std_logic; 
         pout:buffer std_logic;
			test:out std_logic;
			dis,lcd,lcdcontrol:out std_logic_vector(0 to 7)
			); 
end maichong; 


architecture rtl of maichong is   
--component fenpin
--	PORT (clk:IN std_logic;
--      	clk2:BUFFER std_logic );
--end component;
signal control,clk2 : std_logic;
signal pcount:std_logic_vector(0 to 7);
begin  
--u1: fenpin PORT MAP(clk,clk2);

    process(clk,LOAD) --減數模塊，當count不為0時使contorl=1
    variable count:std_logic_vector(0 to 7) :="00000000"; 
    begin 
		
	   if load='1' then 
				count:=D;  --異步置數
      else if (clk'event and clk='1') then
				if count /=0 then
				count:=count-1;
				end if;
				IF count>0 THEN
					control<='1';
				else 
					control<='0';
				end if;
			end if;
		end if;		  
    end process;
	 
	 process(clk,control) --脈沖,control=1時使pout=clk
	 begin
		--pout<='0';
 
        if control ='1' then			
			pout<=clk;   -- pout<=clk;-其他任何地方用clk都改為clk的2或4分頻，做個分頻電路
    	else 
		pout<='0';
		end if;

	 end process;
	 
	 process(pout)  --脈沖計數模塊,將記錄到的總脈沖數更新到pcount中
	 begin
		 if (pout'event and pout='1') then
			pcount<=pcount+1;
		 end if ;
	 end process;
	 
	 process(pcount) --顯示模塊,將pcount的值翻譯為LCD碼
	 begin
	 dis<=pcount;
	 case pcount is
		WHEN "00000000" => lcd <= "11111100" ;--0
		WHEN "00000001" => lcd <= "01100000" ;--1
		WHEN "00000010" => lcd <= "11011010" ;--2
		WHEN "00000011" => lcd <= "11110010" ;--3
		WHEN "00000100" => lcd <= "01100110" ;--4
		WHEN "00000101" => lcd <= "10110110" ;--5
		WHEN "00000110" => lcd <= "10111110" ;--6
		WHEN "00000111" => lcd <= "11100000" ;--7
		WHEN "00001000" => lcd <= "11111110" ;--8
		WHEN "00001001" => lcd <= "11110110" ;--9
		WHEN OTHERS => lcd <= "11111100";
end case;
	 end process;

	 process(control) --測試
	 begin
	 test<=control;
	 end process;
	 
lcdcontrol<="00000001";--前八位片選,最后一位設置小數點


end rtl;