/* *  drivers/mtd/nand/rtc_from4.c * *  Copyright (C) 2004  Red Hat, Inc. * *  Derived from drivers/mtd/nand/spia.c *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) * * $Id: rtc_from4.c,v 1.1.1.1 2007/09/01 10:29:11 hansorblue Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Overview: *   This is a device driver for the AG-AND flash device found on the *   Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4), *   which utilizes the Renesas HN29V1G91T-30 part. *   This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device. */#include <linux/delay.h>#include <linux/kernel.h>#include <linux/init.h>#include <linux/slab.h>#include <linux/rslib.h>#include <linux/module.h>#include <linux/mtd/compatmac.h>#include <linux/mtd/mtd.h>#include <linux/mtd/nand.h>#include <linux/mtd/partitions.h>#include <asm/io.h>/* * MTD structure for Renesas board */static struct mtd_info *rtc_from4_mtd = NULL;#define RTC_FROM4_MAX_CHIPS	2/* HS77x9 processor register defines */#define SH77X9_BCR1	((volatile unsigned short *)(0xFFFFFF60))#define SH77X9_BCR2	((volatile unsigned short *)(0xFFFFFF62))#define SH77X9_WCR1	((volatile unsigned short *)(0xFFFFFF64))#define SH77X9_WCR2	((volatile unsigned short *)(0xFFFFFF66))#define SH77X9_MCR	((volatile unsigned short *)(0xFFFFFF68))#define SH77X9_PCR	((volatile unsigned short *)(0xFFFFFF6C))#define SH77X9_FRQCR	((volatile unsigned short *)(0xFFFFFF80))/* * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor) *//* Address where flash is mapped */#define RTC_FROM4_FIO_BASE	0x14000000/* CLE and ALE are tied to address lines 5 & 4, respectively */#define RTC_FROM4_CLE		(1 << 5)#define RTC_FROM4_ALE		(1 << 4)/* address lines A24-A22 used for chip selection */#define RTC_FROM4_NAND_ADDR_SLOT3	(0x00800000)#define RTC_FROM4_NAND_ADDR_SLOT4	(0x00C00000)#define RTC_FROM4_NAND_ADDR_FPGA	(0x01000000)/* mask address lines A24-A22 used for chip selection */#define RTC_FROM4_NAND_ADDR_MASK	(RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)/* FPGA status register for checking device ready (bit zero) */#define RTC_FROM4_FPGA_SR		(RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)#define RTC_FROM4_DEVICE_READY		0x0001/* FPGA Reed-Solomon ECC Control register */#define RTC_FROM4_RS_ECC_CTL		(RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)#define RTC_FROM4_RS_ECC_CTL_CLR	(1 << 7)#define RTC_FROM4_RS_ECC_CTL_GEN	(1 << 6)#define RTC_FROM4_RS_ECC_CTL_FD_E	(1 << 5)/* FPGA Reed-Solomon ECC code base */#define RTC_FROM4_RS_ECC		(RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)#define RTC_FROM4_RS_ECCN		(RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)/* FPGA Reed-Solomon ECC check register */#define RTC_FROM4_RS_ECC_CHK		(RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)#define RTC_FROM4_RS_ECC_CHK_ERROR	(1 << 7)#define ERR_STAT_ECC_AVAILABLE		0x20/* Undefine for software ECC */#define RTC_FROM4_HWECC	1/* Define as 1 for no virtual erase blocks (in JFFS2) */#define RTC_FROM4_NO_VIRTBLOCKS	0/* * Module stuff */static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);static const struct mtd_partition partition_info[] = {	{	 .name = "Renesas flash partition 1",	 .offset = 0,	 .size = MTDPART_SIZ_FULL},};#define NUM_PARTITIONS 1/* *	hardware specific flash bbt decriptors *	Note: this is to allow debugging by disabling *		NAND_BBT_CREATE and/or NAND_BBT_WRITE * */static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };static struct nand_bbt_descr rtc_from4_bbt_main_descr = {	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,	.offs = 40,	.len = 4,	.veroffs = 44,	.maxblocks = 4,	.pattern = bbt_pattern};static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,	.offs = 40,	.len = 4,	.veroffs = 44,	.maxblocks = 4,	.pattern = mirror_pattern};#ifdef RTC_FROM4_HWECC/* the Reed Solomon control structure */static struct rs_control *rs_decoder;/* *      hardware specific Out Of Band information */static struct nand_ecclayout rtc_from4_nand_oobinfo = {	.eccbytes = 32,	.eccpos = {		   0, 1, 2, 3, 4, 5, 6, 7,		   8, 9, 10, 11, 12, 13, 14, 15,		   16, 17, 18, 19, 20, 21, 22, 23,		   24, 25, 26, 27, 28, 29, 30, 31},	.oobfree = {{32, 32}}};/* Aargh. I missed the reversed bit order, when I * was talking to Renesas about the FPGA. * * The table is used for bit reordering and inversion * of the ecc byte which we get from the FPGA */static uint8_t revbits[256] = {	0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,	0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,	0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,	0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,	0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,	0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,	0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,	0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,	0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,	0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,	0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,	0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,	0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,	0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,	0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,	0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,	0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,	0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,	0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,	0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,	0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,	0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,	0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,	0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,	0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,	0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,	0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,	0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,	0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,	0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,	0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,	0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,};#endif/* * rtc_from4_hwcontrol - hardware specific access to control-lines * @mtd:	MTD device structure * @cmd:	hardware control command * * Address lines (A5 and A4) are used to control Command and Address Latch * Enable on this board, so set the read/write address appropriately. * * Chip Enable is also controlled by the Chip Select (CS5) and * Address lines (A24-A22), so no action is required here. * */static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,				unsigned int ctrl){	struct nand_chip *chip = (mtd->priv);	if (cmd == NAND_CMD_NONE)		return;	if (ctrl & NAND_CLE)		writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);	else		writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);}/* * rtc_from4_nand_select_chip - hardware specific chip select * @mtd:	MTD device structure * @chip:	Chip to select (0 == slot 3, 1 == slot 4) * * The chip select is based on address lines A24-A22. * This driver uses flash slots 3 and 4 (A23-A22). * */static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip){	struct nand_chip *this = mtd->priv;	this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);	this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);	switch (chip) {	case 0:		/* select slot 3 chip */		this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);		this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);		break;	case 1:		/* select slot 4 chip */		this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);		this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);		break;	}}/* * rtc_from4_nand_device_ready - hardware specific ready/busy check * @mtd:	MTD device structure * * This board provides the Ready/Busy state in the status register * of the FPGA.  Bit zero indicates the RDY(1)/BSY(0) signal. * */static int rtc_from4_nand_device_ready(struct mtd_info *mtd){	unsigned short status;	status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));	return (status & RTC_FROM4_DEVICE_READY);}/* * deplete - code to perform device recovery in case there was a power loss * @mtd:	MTD device structure * @chip:	Chip to select (0 == slot 3, 1 == slot 4) * * If there was a sudden loss of power during an erase operation, a * "device recovery" operation must be performed when power is restored * to ensure correct operation.  This routine performs the required steps * for the requested chip. * * See page 86 of the data sheet for details. * */static void deplete(struct mtd_info *mtd, int chip){	struct nand_chip *this = mtd->priv;	/* wait until device is ready */	while (!this->dev_ready(mtd)) ;	this->select_chip(mtd, chip);	/* Send the commands for device recovery, phase 1 */	this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);	this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);	/* Send the commands for device recovery, phase 2 */	this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);	this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);}#ifdef RTC_FROM4_HWECC/* * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function * @mtd:	MTD device structure * @mode:	I/O mode; read or write * * enable hardware ECC for data read or write * */static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode){	volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);	unsigned short status;	switch (mode) {	case NAND_ECC_READ:		status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;		*rs_ecc_ctl = status;		break;	case NAND_ECC_READSYN:		status = 0x00;		*rs_ecc_ctl = status;		break;