LIBRARY IEEE;												//調用標準庫文件
use  ieee.std_logic_1164.all ;
use  ieee.std_logic_unsigned.all ;
entity  add16 is 												//定義實體
   port(												//定義端口
      cin : in std_logic  ;
      a , b : in std_logic_vector(15 downto 0) ;
      s :  out std_logic_vector(15 downto 0)) ;
 end add16  ;
architecture behavior of add16 is
   signal st : std_logic_vector(16 downto 0) ;
   signal ag,bg : std_logic_vector(16 downto 0) ;
begin 
   ag<='0'&a ;
   bg<='0'&b ;
   st<=ag+bg+cin  ;  
   s<=st(15 downto 0) ;
end  behavior  ;