?? bell.rpt
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Project Information i:\workhard\bell.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/16/2008 17:02:36
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
bell EPF10K10LC84-3 23 17 0 0 0 % 46 7 %
User Pins: 23 17 0
Project Information i:\workhard\bell.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'Second7'
Warning: Ignored unnecessary INPUT pin 'Second6'
Warning: Ignored unnecessary INPUT pin 'Second5'
Warning: Ignored unnecessary INPUT pin 'Second4'
Warning: Ignored unnecessary INPUT pin 'Second3'
Warning: Ignored unnecessary INPUT pin 'Second2'
Warning: Ignored unnecessary INPUT pin 'Second1'
Project Information i:\workhard\bell.rpt
** FILE HIERARCHY **
|counter24:SU2|
|counter24:SU2|lpm_add_sub:296|
|counter24:SU2|lpm_add_sub:296|addcore:adder|
|counter24:SU2|lpm_add_sub:296|altshift:result_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:296|altshift:carry_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:296|altshift:oflow_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:297|
|counter24:SU2|lpm_add_sub:297|addcore:adder|
|counter24:SU2|lpm_add_sub:297|altshift:result_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:297|altshift:carry_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:297|altshift:oflow_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:298|
|counter24:SU2|lpm_add_sub:298|addcore:adder|
|counter24:SU2|lpm_add_sub:298|altshift:result_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:298|altshift:carry_ext_latency_ffs|
|counter24:SU2|lpm_add_sub:298|altshift:oflow_ext_latency_ffs|
|cmp:SU3|
|cmp:SU4|
|counter60:SU1|
|counter60:SU1|counter10:UC0|
|counter60:SU1|counter10:UC0|lpm_add_sub:45|
|counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|
|counter60:SU1|counter10:UC0|lpm_add_sub:45|altshift:result_ext_latency_ffs|
|counter60:SU1|counter10:UC0|lpm_add_sub:45|altshift:carry_ext_latency_ffs|
|counter60:SU1|counter10:UC0|lpm_add_sub:45|altshift:oflow_ext_latency_ffs|
|counter60:SU1|counter6:UC1|
|counter60:SU1|counter6:UC1|lpm_add_sub:45|
|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|
|counter60:SU1|counter6:UC1|lpm_add_sub:45|altshift:result_ext_latency_ffs|
|counter60:SU1|counter6:UC1|lpm_add_sub:45|altshift:carry_ext_latency_ffs|
|counter60:SU1|counter6:UC1|lpm_add_sub:45|altshift:oflow_ext_latency_ffs|
|cmp:SU5|
|cmp:SU6|
Device-Specific Information: i:\workhard\bell.rpt
bell
***** Logic for device 'bell' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R C R S S R R R O
S E t E e e E M E E N
e _ S r S V t t G S i S S F
H t 5 _ E l E C H H H _ N E n E E _ ^
o _ 0 1 R B R C o r _ o M D R u R R # D n
u H 0 k V e V I u k 1 u i I V t V V T O C
r r H H E l E N r e H r n N E e E E C N E
2 1 z z D l D T 7 y z 0 3 T D 6 D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
RESERVED | 16 70 | RESERVED
RESERVED | 17 69 | Set_Min2
RESERVED | 18 68 | GNDINT
RESERVED | 19 67 | Set_Hr0
VCCINT | 20 66 | Minute3
Set_Hr2 | 21 65 | Set_Hr3
Set_Hr4 | 22 EPF10K10LC84-3 64 | Hour3
Set_Hr6 | 23 63 | VCCINT
Set_Hr7 | 24 62 | Minute5
Set_Hr5 | 25 61 | Set_Min0
GNDINT | 26 60 | Set_Min5
Minute2 | 27 59 | Set_Min1
Minute4 | 28 58 | Set_Min6
Minute1 | 29 57 | #TMS
Hour1 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | Minute0
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ S A H R R V G S H H V G R R R M R S S
C n e l o E E C N e o o C N E E E i E e e
C C c a u S S C D t u u C D S S S n S t t
I O o r r E E I I M r r I I E E E u E _ _
N N n m 6 R R N N i 4 5 N N R R R t R M M
T F d _ V V T T n T T V V V e V i i
I 0 c E E k E E E 7 E n n
G l D D e D D D D 4 7
o y
c
k
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: i:\workhard\bell.rpt
bell
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
B4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
B6 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
B8 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
C13 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C22 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 34/53 ( 64%)
Total logic cells used: 46/576 ( 7%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.52/4 ( 88%)
Total fan-in: 162/2304 ( 7%)
Total input pins required: 23
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 46
Total flipflops required: 16
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 16/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 8 0 8 0 7 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 8 0 3 0 0 19/0
Total: 0 8 0 8 0 7 0 4 0 0 0 0 0 8 0 0 0 0 0 0 8 0 3 0 0 46/0
Device-Specific Information: i:\workhard\bell.rpt
bell
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
6 - - - 04 INPUT 0 0 0 1 CtrlBell
84 - - - -- INPUT 0 0 0 1 Hour0
30 - - C -- INPUT 0 0 0 1 Hour1
11 - - - 01 INPUT 0 0 0 1 Hour2
64 - - B -- INPUT 0 0 0 1 Hour3
43 - - - -- INPUT 0 0 0 1 Hour4
44 - - - -- INPUT 0 0 0 1 Hour5
37 - - - 09 INPUT 0 0 0 1 Hour6
3 - - - 12 INPUT 0 0 0 1 Hour7
54 - - - 21 INPUT 0 0 0 1 Minute0
29 - - C -- INPUT 0 0 0 1 Minute1
27 - - C -- INPUT 0 0 0 1 Minute2
66 - - B -- INPUT 0 0 0 1 Minute3
28 - - C -- INPUT 0 0 0 1 Minute4
62 - - C -- INPUT 0 0 0 1 Minute5
80 - - - 23 INPUT 0 0 0 1 Minute6
50 - - - 17 INPUT 0 0 0 1 Minute7
35 - - - 06 INPUT 0 0 0 1 Second0
2 - - - -- INPUT 0 0 0 9 SetHrkey
42 - - - -- INPUT 0 0 0 4 SetMinkey
1 - - - -- INPUT G 0 0 0 0 _1Hz
8 - - - 03 INPUT 0 0 0 1 _1kHz
9 - - - 02 INPUT 0 0 0 1 _500Hz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: i:\workhard\bell.rpt
bell
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
36 - - - 07 OUTPUT 0 1 0 0 Alarm_clock
67 - - B -- OUTPUT 0 1 0 0 Set_Hr0
10 - - - 01 OUTPUT 0 1 0 0 Set_Hr1
21 - - B -- OUTPUT 0 1 0 0 Set_Hr2
65 - - B -- OUTPUT 0 1 0 0 Set_Hr3
22 - - B -- OUTPUT 0 1 0 0 Set_Hr4
25 - - B -- OUTPUT 0 1 0 0 Set_Hr5
23 - - B -- OUTPUT 0 1 0 0 Set_Hr6
24 - - B -- OUTPUT 0 1 0 0 Set_Hr7
61 - - C -- OUTPUT 0 1 0 0 Set_Min0
59 - - C -- OUTPUT 0 1 0 0 Set_Min1
69 - - A -- OUTPUT 0 1 0 0 Set_Min2
83 - - - 13 OUTPUT 0 1 0 0 Set_Min3
52 - - - 19 OUTPUT 0 1 0 0 Set_Min4
60 - - C -- OUTPUT 0 1 0 0 Set_Min5
58 - - C -- OUTPUT 0 1 0 0 Set_Min6
53 - - - 20 OUTPUT 0 1 0 0 Set_Min7
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