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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.109 ns
From           : SinCtrl
To             : sld_signaltap:singt|acq_trigger_in_reg[7]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.744 ns
From           : SDelay:Delayi|result[0]
To             : SinOut[5]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.629 ns
From           : SinCtrl
To             : SinOut[5]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.540 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : 21.121 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : 128.90 MHz ( period = 7.758 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : 43.008 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : 143.02 MHz ( period = 6.992 ns )
From           : lpm_rom:SinLUTi|altrom:srom|altsyncram:rom_block|altsyncram_ch01:auto_generated|ram_block1a1~porta_address_reg9
To             : SDelay:Delayi|result[1]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : 0.861 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|holdff
To             : sld_signaltap:singt|acq_data_in_pipe_reg[2][6]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'altera_internal_jtag~TCKUTAP'
Slack          : 0.867 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[12]
To             : sld_signaltap:singt|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[11]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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