?? dspregdefine.h
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#ifndef _DSPREGDEFINE_H
#define _DSPREGDEFINE_H
//**** Map Interrupt Registers to Data Page Addresses
#define IMR 0x0000 // interrupt mask reg
#define IFR 0x0001 // interrupt flag reg
// 0x0002~0x0005 Reserved for testing
#define ST0 0x0006 // CPU status reg0
#define ST1 0x0007 // CPU status reg1
#define A 0x0008 // CPU Accumulator A low word (15–0)
#define AL 0x0008 // CPU Accumulator A low word (15–0)
#define AH 0x0009 // CPU Accumulator A high word (31–16)
#define AG 0x000A // CPU Accumulator A guard bits (39–32)
#define B 0x000B // CPU Accumulator B low word (15–0)
#define BL 0x000B // CPU Accumulator B low word (15–0)
#define BH 0x000C // CPU Accumulator B high word (31–16)
#define BG 0x000D // CPU Accumulator B guard bits (39–32
#define TREG 0x000E // CPU temporary reg
#define TRN 0x000F // CPU transition reg
#define AR0 0x0010 // CPU auxiliary reg0
#define AR1 0x0011 // CPU auxiliary reg1
#define AR2 0x0012 // CPU auxiliary reg2
#define AR3 0x0013 // CPU auxiliary reg3
#define AR4 0x0014 // CPU auxiliary reg4
#define AR5 0x0015 // CPU auxiliary reg5
#define AR6 0x0016 // CPU auxiliary reg6
#define AR7 0x0017 // CPU auxiliary reg7
#define SP 0x0018 // CPU stack pointer reg
#define BK 0x0019 // CPU circular buffer size reg
#define BRC 0x001A // CPU block repeat counter
#define RSA 0x001B // CPU block repeat start address
#define REA 0x001C // CPU block repeat end address
#define PMST 0x001D // processor mode status reg
#define XPC 0x001E // extended program page reg
//0x001Fh Reserved
//************************************************
//*****Peripheral Memory-Mapped Registers*******
//************************************************
//******** Map McBSP0 Registers to Data Page Addresses
#define McBSP0_DRR2 0x0020 // McBSP0 data Rx reg2
#define McBSP0_DRR1 0x0021 // McBSP0 data Rx reg1
#define McBSP0_DXR2 0x0022 // McBSP0 data Tx reg2
#define McBSP0_DXR1 0x0023 // McBSP0 data Tx reg1
//******** Map Timer0 Registers to Data Page Addresses
#define TIM 0x0024 // timer0 reg
#define PRD 0x0025 // timer0 period reg
#define TCR 0x0026 // timer0 control reg
//0x0027h Reserved
#define SWWSR 0x0028 // software wait state reg
#define BSCR 0x0029 // bank switching control reg
//0x002a Reserved
#define SWCR 0x002B // software wait state control reg
//******** Map HPI Registers to Data Page Addresses
#define HPIC 0x002C // HPI control reg
//0x002d~0x002f Reserved
//******** Map Timer1 Registers to Data Page Addresses
#define TIM1 0x0030 // timer1 reg
#define PRD1 0x0031 // timer1 period reg
#define TCR1 0x0032 // timer1 control reg
//0x0033~0x0037h Reserved
#define McBSP0_SPSA 0x0038 // McBSP0 sub bank addr reg
#define McBSP0_SPSD 0x0039 // McBSP0 sub bank data reg
//0x003a~0x003b Reserved
//******** Map General IO Port (Pins) Registers to Data Page Addresses
#define GPIOCR 0x003C // GP I/O Pins Control Reg
#define GPIOSR 0x003D // GP I/O Pins Status Reg
//0x003e~0x003f Reserved
//******** Map McBSP1 Registers to Data Page Addresses
#define McBSP1_DRR2 0x0040 // McBSP1 data Rx reg2
#define McBSP1_DRR1 0x0041 // McBSP1 data Rx reg1
#define McBSP1_DXR2 0x0042 // McBSP1 data Tx reg2
#define McBSP1_DXR1 0x0043 // McBSP1 data Tx reg1
//0x0044~0x0047h Reserved
#define McBSP1_SPSA 0x0048 // McBSP1 sub bank addr reg
#define McBSP1_SPSD 0x0049 // McBSP1 sub bank data reg
//0x004a~0x0053h Reserved
//******* Map DMA Registers to Data Page Addresses
#define DMPREC 0x0054 // DMA channel priority and ebanle control
#define DMSA 0x0055 // DMA subbank address reg
#define DMSDI 0x0056 // DMA subbank data reg with autoincrement
#define DMSDN 0x0057 // DMA subbank data reg without autoincrement
#define CLKMD 0x0058 // clock mode reg
//0x0059~0x005fh Reserved
//************************************************************************
//** Sub Bank Address Definations
//************************************************************************
//******** McBSP Sub Bank Register Addresses
#define SPCR1 0x0000 // McBSP Ser Port Ctrl Reg1
#define SPCR2 0x0001 // McBSP Ser Port Ctrl Reg2
#define RCR1 0x0002 // McBSP Rx Ctrl Reg1
#define RCR2 0x0003 // McBSP Rx Ctrl Reg2
#define XCR1 0x0004 // McBSP Tx Ctrl Reg1
#define XCR2 0x0005 // McBSP Tx Ctrl Reg2
#define SRGR1 0x0006 // McBSP Sample Rate Gen Reg1
#define SRGR2 0x0007 // McBSP Sample Rate Gen Reg2
#define MCR1 0x0008 // McBSP Multichannel Reg1
#define MCR2 0x0009 // McBSP Multichannel Reg2
#define RCERA 0x000A // McBSP Rx Chan Enable Reg PartA
#define RCERB 0x000B // McBSP Rx Chan Enable Reg PartB
#define XCERA 0x000C // McBSP Tx Chan Enable Reg PartA
#define XCERB 0x000D // McBSP Tx Chan Enable Reg PartB
#define PCR 0x000E // McBSP Pin Ctrl Reg
//******* DMA Sub Bank Register Addresses
#define DMSRC0 0x0000 // DMA channel0 source address reg
#define DMDST0 0x0001 // DMA channel0 destination address reg
#define DMCTR0 0x0002 // DMA channel0 element count reg
#define DMSFC0 0x0003 // DMA channel0 sync sel & frame count reg
#define DMMCR0 0x0004 // DMA channel0 transfer mode cntrl reg
#define DMSRC1 0x0005 // DMA channel1 source address reg
#define DMDST1 0x0006 // DMA channel1 destination address reg
#define DMCTR1 0x0007 // DMA channel1 element count reg
#define DMSFC1 0x0008 // DMA channel1 sync sel & frame count reg
#define DMMCR1 0x0009 // DMA channel1 transfer mode cntrl reg
#define DMSRC2 0x000A // DMA channel2 source address reg
#define DMDST2 0x000B // DMA channel2 destination address reg
#define DMCTR2 0x000C // DMA channel2 element count reg
#define DMSFC2 0x000D // DMA channel2 sync sel & frame count reg
#define DMMCR2 0x000E // DMA channel2 transfer mode cntrl reg
#define DMSRC3 0x000F // DMA channel3 source address reg
#define DMDST3 0x0010 // DMA channel3 destination address reg
#define DMCTR3 0x0011 // DMA channel3 element count reg
#define DMSFC3 0x0012 // DMA channel3 sync sel & frame count reg
#define DMMCR3 0x0013 // DMA channel3 transfer mode cntrl reg
#define DMARC4 0x0014 // DMA channel4 source address reg
#define DMDST4 0x0015 // DMA channel4 destination address reg
#define DMCTR4 0x0016 // DMA channel4 element count reg
#define DMSFC4 0x0017 // DMA channel4 sync sel & frame count reg
#define DMMCR4 0x0018 // DMA channel4 transfer mode cntrl reg
#define DMSRC5 0x0019 // DMA channel5 source address reg
#define DMDST5 0x001A // DMA channel5 destination address reg
#define DMCTR5 0x001B // DMA channel5 element count reg
#define DMSFC5 0x001C // DMA channel5 sync sel & frame count reg
#define DMMCR5 0x001D // DMA channel5 transfer mode cntrl reg
#define DMSRCP 0x001E // DMA source prog page address
#define DMDSTP 0x001F // DMA destination prog page address
#define DMIDX0 0x0020 // DMA element index address reg0
#define DMIDX1 0x0021 // DMA element index address reg1
#define DMFRI0 0x0022 // DMA frame index reg0
#define DMFRI1 0x0023 // DMA frame index reg1
#define DMGSA 0x0024 // DMA global source address reload reg
#define DMGDA 0x0025 // DMA global destination address reload reg
#define DMGCR 0x0026 // DMA global counter reload reg
#define DMGFR 0x0027 // DMA global frame count reload reg
/*
***********************************************************************
** End of File MMRegs.h
************************************************************************
*/
#endif
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