?? register_w_target.v
字號:
module REGISTER_W_TARGET(in, w, out, rst, clk); input [1:0] in; wire [1:0] in; input [0:0] w; wire [0:0] w; output [1:0] out; reg [1:0] out; input rst; wire rst; input clk; wire clk; always @(posedge clk or posedge rst) begin : reg_thread if (rst == 1) out <= 2'b00; else begin if (w[1'b0] == 1) out <= in; end endendmodule
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