module INPUT_CTRL(clk, rst, my_address, ch0, ch1, req, ack, data, out_select, request_switch, data_out, out_req, out_ack);    input clk;    wire clk;    input rst;    wire rst;    input [7:0] my_address;    wire [7:0] my_address;    input ch0;    wire ch0;    input ch1;    wire ch1;    input req;    wire req;    output ack;    reg ack;    input [17:0] data;    wire [17:0] data;    output [1:0] out_select;    reg [1:0] out_select;    output request_switch;    reg request_switch;    output [17:0] data_out;    reg [17:0] data_out;    output out_req;    reg out_req;    input out_ack;    wire out_ack;    reg [17:0] data_latch;    reg latch;    reg ack_v;    reg out_req_v;    reg header_select_v;    reg request_switch_v;    reg latch_v;    reg [2:0] next_state;    reg end_of_packet;    reg [2:0] current_state;    reg header_select;    reg start_of_packet;    reg [7:0] my_addr;    reg [17:0] __tmp61;    reg [17:0] d;    reg [7:0] bvaddr;    reg [7:0] still_to_go;    reg [1:0] out_select_n;    reg [1:0] bFT;    reg [7:0] bXA;    reg [7:0] bYA;    reg [1:0] flit_type;    reg [7:0] xaddr;    reg [7:0] yaddr;    reg end_of_route;    reg [7:0] xaddr_out;    reg [7:0] yaddr_out;    reg [7:0] bXAout;    reg [7:0] bYAout;    reg [17:0] hout;    reg [17:0] header;        always @(posedge clk)        begin : dlatch            if (latch)                data_latch <= data;        end        always @(current_state or req or out_ack or start_of_packet or end_of_packet)        begin : control_logic            ack_v = 0;            out_req_v = 0;            header_select_v = 0;            request_switch_v = 0;            latch_v = 0;            next_state = 3'b000;            case (current_state) //synopsys parallel_case full_case            0:              if (req)            begin                latch_v = 1;                next_state = 3'b001;                header_select_v = 1;            end            else                next_state = 3'b000;            1:  begin                request_switch_v = 1;                header_select_v = 1;                ack_v = out_ack;                out_req_v = req;                if (out_ack)                    next_state = 3'b010;                else                    next_state = 3'b001;            end            2:  begin                request_switch_v = 1;                if (out_ack)                    next_state = 3'b010;                else                    next_state = 3'b011;            end            3:  begin                request_switch_v = 1;                if (req)                begin                    next_state = 3'b100;                    header_select_v = 0;                    latch_v = 1;                end                else                    next_state = 3'b011;            end            4:  begin                request_switch_v = 1;                header_select_v = 0;                ack_v = out_ack;                out_req_v = req;                if (out_ack)                begin                    if (end_of_packet)                        next_state = 3'b101;                    else                        next_state = 3'b010;                end                else                    next_state = 3'b100;            end            5:  begin                request_switch_v = 1;                if (out_ack)                    next_state = 3'b101;                else                    next_state = 3'b000;            end            endcase            ack = ack_v;            out_req = out_req_v;            header_select = header_select_v;            request_switch = request_switch_v;            latch = latch_v;        end        always @(posedge clk or posedge rst)        begin : control_change_state            if (rst)                current_state <= 3'b000;            else                current_state <= next_state;        end        always @(data or data_latch or latch or my_address or ch0 or ch1)        begin : route_select            my_addr = my_address;            if (latch)                __tmp61 = data;            else                __tmp61 = data_latch;            d = __tmp61;            bvaddr = d[15:8];            still_to_go = bvaddr;            out_select_n = 2'b00;            if (still_to_go == 8'b00000000)                out_select_n = 2'b11;            else            begin                if (my_addr == 8'b00000000 && ch0 || ch1)                    out_select_n = 2'b10;                else                    out_select_n = 2'b01;            end        end        always @(posedge clk)        begin : switch_out_select            if (header_select)                out_select <= out_select_n;        end        always @(data_latch or end_of_route)        begin : header_adjust            bFT = data_latch[17:16];            bXA = data_latch[15:8];            bYA = data_latch[7:0];            flit_type = bFT;            xaddr = bXA;            yaddr = bYA;            if (xaddr == 8'b00000000)            begin                end_of_route = 1;                xaddr_out = yaddr;                yaddr_out = 8'b00000000;            end            else            begin                end_of_route = 0;                xaddr_out = xaddr - 1;                yaddr_out = yaddr;            end            case (flit_type) //synopsys parallel_case            1:  begin                start_of_packet = 1;                end_of_packet = 0;            end            2:  begin                start_of_packet = 0;                end_of_packet = 1;            end            default : begin                 start_of_packet = 0;                end_of_packet = 0;                end            endcase            bXAout = xaddr_out;            bYAout = yaddr_out;            hout[17:16] = bFT;            hout[15:8] = bXAout;            hout[7:0] = bYAout;            header = hout;        end        always @(data_latch or header or header_select)        begin : data_select            if (header_select)                data_out = header;            else                data_out = data_latch;        endendmodule