module DATA_CACHE(addr, din, dout, memwait, w, r, clk, en, mem_addr, mem_din, mem_dout, mem_ww, mem_wb, mem_r, mem_rdy);    input [31:0] addr;    wire [31:0] addr;    input [31:0] din;    wire [31:0] din;    output [31:0] dout;    output memwait;    input [1:0] w;    wire [1:0] w;    input [1:0] r;    wire [1:0] r;    input clk;    wire clk;    input [0:0] en;    wire [0:0] en;    output [31:0] mem_addr;    output [31:0] mem_din;    input [31:0] mem_dout;    wire [31:0] mem_dout;    output mem_ww;    output mem_wb;    output mem_r;    input mem_rdy;    wire mem_rdy;    wire reg_disable;    wire current_reg;    wire [1:0] w_reg;    wire [1:0] w_current;    wire [1:0] r_reg;    wire [1:0] r_current;    wire [31:0] din_reg;    wire [31:0] data_current;    wire [31:0] addr_reg;    wire [31:0] addr_current;    wire valid;    wire [19:0] tag_out;    wire [19:0] tag_reg;    wire cache_en;    wire cache_we;    wire rewrite;    wire byte_rpl;    wire [1:0] fetch_word;    wire fetch_word_rdy;    wire [31:0] data_mem_out;    wire [1:0] byte_reg;    wire [19:0] tag_in;    wire [7:0] index;    wire [7:0] index_reg;    wire [1:0] offset;    wire [1:0] offset_reg;    wire [1:0] byte;    wire valid_select;    wire [31:0] data_mem_in;    REG_DISABLE register_disable(.memwait(memwait), .en(en), .disable__22(reg_disable));    REG2_SEL w_register(.clk(clk), .disable__20(reg_disable), .select(current_reg), .din(w), .dout(w_reg), .dout_select(w_current));    REG2_SEL r_register(.clk(clk), .disable__20(reg_disable), .select(current_reg), .din(r), .dout(r_reg), .dout_select(r_current));    DWORD_REG_SEL data_register(.clk(clk), .disable__18(reg_disable), .select(current_reg), .din(din), .dout(din_reg), .dout_select(data_current));    DWORD_REG_SEL addr_register(.clk(clk), .disable__18(reg_disable), .select(current_reg), .din(addr), .dout(addr_reg), .dout_select(addr_current));    CACHE_MISS_CTRL miss_ctrl(.clk(clk), .en(en), .cache_valid(valid), .cache_tag(tag_out), .addr_tag(tag_reg), .cache_en(cache_en), .cache_we(cache_we), .w(w), .r(r), .miss_wait(memwait), .rewrite(rewrite), .byte_rpl(byte_rpl), .current_reg(current_reg), .mem_ww(mem_ww), .mem_wb(mem_wb), .mem_r(mem_r), .mem_rdy(mem_rdy), .din(data_current), .addr(addr_current), .mem_din(mem_din), .mem_addr(mem_addr), .fetch_word(fetch_word), .fetch_word_rdy(fetch_word_rdy));    CACHE_BYTE_SELECT byte_select(.din(data_mem_out), .r(r_reg), .byte(byte_reg), .dout(dout));    CACHE_ADDR_SPLIT addr_split(.addr(addr_current), .addr_reg(addr_reg), .fetch_word(fetch_word), .fetch_word_rdy(fetch_word_rdy), .tag_rewrite(tag_out), .rewrite(rewrite), .tag(tag_in), .tag_reg(tag_reg), .index(index), .index_reg(index_reg), .offset(offset), .offset_reg(offset_reg), .byte(byte), .byte_reg(byte_reg));    CACHE_DIN_SELECT din_select(.din_data(data_current), .din_data_reg(din_reg), .din_fetch(mem_dout), .din_out(data_mem_out), .rewrite(rewrite), .rewrite_valid(valid), .byte_rpl(byte_rpl), .w(w), .byte(byte), .fetch_word_rdy(fetch_word_rdy), .valid(valid_select), .data(data_mem_in));    CACHE_MEMORY cache_memory(.clk(clk), .din(data_mem_in), .valid_in(valid_select), .tagi(tag_in), .index(index), .offset(offset), .we(cache_we), .en(cache_en), .dout(data_mem_out), .tago(tag_out), .valid(valid));endmodule