/* mips-opc.c -- MIPS opcode list.   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000   Free Software Foundation, Inc.   Contributed by Ralph Campbell and OSF   Commented and modified by Ian Lance Taylor, Cygnus Support   Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.This file is part of GDB, GAS, and the GNU binutils.GDB, GAS, and the GNU binutils are free software; you can redistributethem and/or modify them under the terms of the GNU General PublicLicense as published by the Free Software Foundation; either version1, or (at your option) any later version.GDB, GAS, and the GNU binutils are distributed in the hope that theywill be useful, but WITHOUT ANY WARRANTY; without even the impliedwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  Seethe GNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with this file; see the file COPYING.  If not, write to the FreeSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */#include <stdio.h>#include "sysdep.h"#include "opcode/mips.h"/* Short hand so the lines aren't too long.  */#define LDD     INSN_LOAD_MEMORY_DELAY#define LCD	INSN_LOAD_COPROC_DELAY#define UBD     INSN_UNCOND_BRANCH_DELAY#define CBD	INSN_COND_BRANCH_DELAY#define COD     INSN_COPROC_MOVE_DELAY#define CLD	INSN_COPROC_MEMORY_DELAY#define CBL	INSN_COND_BRANCH_LIKELY#define TRAP	INSN_TRAP#define SM	INSN_STORE_MEMORY#define WR_d    INSN_WRITE_GPR_D#define WR_t    INSN_WRITE_GPR_T#define WR_31   INSN_WRITE_GPR_31#define WR_D    INSN_WRITE_FPR_D#define WR_T	INSN_WRITE_FPR_T#define WR_S	INSN_WRITE_FPR_S#define RD_s    INSN_READ_GPR_S#define RD_b    INSN_READ_GPR_S#define RD_t    INSN_READ_GPR_T#define RD_S    INSN_READ_FPR_S#define RD_T    INSN_READ_FPR_T#define RD_R	INSN_READ_FPR_R#define WR_CC	INSN_WRITE_COND_CODE#define RD_CC	INSN_READ_COND_CODE#define RD_C0   INSN_COP#define RD_C1	INSN_COP#define RD_C2   INSN_COP#define RD_C3   INSN_COP#define WR_C0   INSN_COP#define WR_C1	INSN_COP#define WR_C2   INSN_COP#define WR_C3   INSN_COP#define WR_HI	INSN_WRITE_HI#define RD_HI	INSN_READ_HI#define MOD_HI  WR_HI|RD_HI#define WR_LO	INSN_WRITE_LO#define RD_LO	INSN_READ_LO#define MOD_LO  WR_LO|RD_LO#define WR_HILO WR_HI|WR_LO#define RD_HILO RD_HI|RD_LO#define MOD_HILO WR_HILO|RD_HILO#define IS_M    INSN_MULT#define I1	INSN_ISA1#define I2	INSN_ISA2#define I3	INSN_ISA3#define I4	INSN_ISA4#define I5	INSN_ISA5#define I32	INSN_ISA32#define I64     INSN_ISA64#define P3	INSN_4650#define L1	INSN_4010#define V1      INSN_4100#define T3      INSN_3900#define G1      (T3             \                 )#define G2      (T3                   \                 )#define G3 (I4             \            )#define G6      INSN_GP32/* The order of overloaded instructions matters.  Label arguments and   register arguments look the same. Instructions that can have either   for arguments must apear in the correct order in this table for the   assembler to pick the right one. In other words, entries with   immediate operands must apear after the same instruction with   registers.   Many instructions are short hand for other instructions (i.e., The   jal <register> instruction is short for jalr <register>).  */const struct mips_opcode mips_builtin_opcodes[] ={/* These instructions appear first so that the disassembler will find   them first.  The assemblers uses a hash table based on the   instruction name anyhow.  *//* name,    args,	match,	    mask,	pinfo,          	membership */{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	I32|G3	},{"nop",     "",         0x00000000, 0xffffffff, 0,              	I1      },{"ssnop",   "",         0x00000040, 0xffffffff, 0,              	I32	},{"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			I1	}, /* addiu */{"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			I1	}, /* ori */{"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		I1	},{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1|G6	},/* or */{"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,		I3	},/* daddu */{"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,		I1	},/* addu */{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1	},/* or */{"b",       "p",	0x10000000, 0xffff0000,	UBD,			I1	},/* beq 0,0 */{"b",       "p",	0x04010000, 0xffff0000,	UBD,			I1	},/* bgez 0 */{"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,		I1	},/* bgezal 0*/{"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		I1	},{"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		I1	},{"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		I1	},{"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		I5	},{"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},{"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		I1	},{"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},{"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},{"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},{"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		I1	},{"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		I1	},{"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},{"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		I1	},{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	I5	},{"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},{"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		I1	},{"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		I1	},/* b is at the top of the table.  *//* bal is at the top of the table.  */{"bc0f",    "p",	0x41000000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc0fl",   "p",	0x41020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},{"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},{"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},{"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},{"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"bc3f",    "p",	0x4d000000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc3fl",   "p",	0x4d020000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"bc0t",    "p",	0x41010000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc0tl",   "p",	0x41030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		I1	},{"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	I4|I32	},{"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		I2|T3	},{"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	I4|I32	},{"bc2t",    "p",	0x49010000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc2tl",   "p",	0x49030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"bc3t",    "p",	0x4d010000, 0xffff0000,	CBD|RD_CC,		I1	},{"bc3tl",   "p",	0x4d030000, 0xffff0000,	CBL|RD_CC,		I2|T3	},{"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,		I1	},{"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},{"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t,		I1	},{"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		I1	},{"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t,		I2|T3	},{"beql",    "s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		I2	},{"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		I1	},{"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,		I1	},{"bgel",    "s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		I2	},{"bgel",    "s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		I2	},{"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,		I1	},{"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,		I1	},{"bgeul",   "s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		I2	},{"bgeul",   "s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		I2	},{"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s,		I1	},{"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},{"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,		I1	},{"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},{"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO,		I1	},{"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,		I1	},{"bgtl",    "s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		I2	},{"bgtl",    "s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		I2	},{"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,		I1	},{"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,		I1	},{"bgtul",   "s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		I2	},{"bgtul",   "s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		I2	},{"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s,		I1	},{"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},{"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO,		I1	},{"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,		I1	},{"blel",    "s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		I2	},{"blel",    "s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		I2	},{"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,		I1	},{"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,		I1	},{"bleul",   "s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		I2	},{"bleul",   "s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		I2	},{"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s,		I1	},{"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},{"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO,		I1	},{"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,		I1	},{"bltl",    "s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		I2	},{"bltl",    "s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		I2	},{"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,		I1	},{"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,		I1	},{"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		I2	},{"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		I2	},{"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,		I1	},{"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,		I2|T3	},