echoecho --- File add.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog add.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File alu.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog alu.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File aluctrl.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog aluctrl.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File bram8k.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog bram8k.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File branch.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog branch.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File bregisterfile16.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog bregisterfile16.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File brom4k.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog brom4k.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File ctrl.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog ctrl.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File decoder.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog decoder.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File hazard.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog hazard.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File imm2word.cppechocompile_systemc -rtl -cpp_options " -I. -DBRAM -DBROM -DBREG -DSPYING -DVERILOG" -rtl_format Verilog imm2word.cppechoecho --- File memdev.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog memdev.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File mux.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog mux.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File shift.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog shift.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File signextend.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog signextend.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File xlxram.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog xlxram.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File top.hechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog top.hif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File benif.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog benif.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File xram.hechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog xram.hif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File cache.hechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog cache.hif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File cache_ctrl.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog cache_ctrl.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File cache_bram.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog cache_bram.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }echoecho --- File cache_mainmem.cppechocompile_systemc -rtl -cpp_options " -I. -DVERILOG -DNCACHE" -rtl_format Verilog cache_mainmem.cppif( dc_shell_status == 0 ) { exit 1; } else { echo OK; }sh rm RAMB16_S9_S9.v RAMB16_S36_S36.v RAMB4_S8_S8.v RAMB4_S16_S16.vexit 0