?? digital_clk.map.rpt
字號:
Analysis & Synthesis report for digital_clk
Thu Dec 25 14:27:17 2008
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Files Read
9. Analysis & Synthesis Resource Usage Summary
10. WYSIWYG Cells
11. General Register Statistics
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 25 14:27:17 2008 ;
; Revision Name ; digital_clk ;
; Top-level Entity Name ; digital_clk ;
; Family ; FLEX10K ;
; Total logic elements ; 237 ;
; Total pins ; 21 ;
; Total memory bits ; 0 ;
+-----------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+------------------------------------------------------+--------------+---------------+
; Top-level entity name ; digital_clk ; ;
; Family name ; FLEX10K ; Stratix ;
; Auto Resource Sharing ; Off ; Off ;
; Auto RAM Replacement ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Carry Chains ; On ; On ;
; Cascade Chain Length ; 2 ; 2 ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Auto Packed Registers ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Auto Implement in ROM ; Off ; Off ;
; Auto Global Register Control Signals ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Clock ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; State Machine Processing ; Auto ; Auto ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 1 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
digital_clk
|-- lpm_counter:clock_h_rtl_1
|-- alt_counter_f10ke:wysi_counter
|-- lpm_counter:clock_m_rtl_3
|-- alt_counter_f10ke:wysi_counter
|-- lpm_counter:count_rtl_4
|-- alt_counter_f10ke:wysi_counter
|-- lpm_counter:hour_rtl_0
|-- alt_counter_f10ke:wysi_counter
|-- lpm_counter:i75_rtl_5
|-- alt_counter_f10ke:wysi_counter
|-- lpm_counter:i109_rtl_7
|-- alt_counter_f10ke:wysi_counter
|-- lpm_divide:i_rtl_8
|-- sign_div_unsign:divider
|-- lpm_add_sub:adder
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
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