+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 59    ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 0     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 14    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Dec 25 14:27:12 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk
Info: Found 2 design units and 1 entities in source file digital_clk.vhd
    Info: Found design unit 1: digital_clk-one
    Info: Found entity 1: digital_clk
Warning: VHDL Process Statement warning at digital_clk.vhd(111): signal sec is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(112): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(113): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(114): signal clk1hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(115): signal mclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(116): signal hclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal clock_m is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(118): signal clock_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(119): signal clk2hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(125): signal sec is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(126): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(127): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(128): signal clk1hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(129): signal mclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(132): signal sec is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(133): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(134): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(135): signal clk1hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(137): signal hclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(139): signal sec is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(140): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(141): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(143): signal mclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(144): signal hclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(147): signal clock_m is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(148): signal clock_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(149): signal clk1hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(150): signal mclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(151): signal hclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(161): signal clock_m is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(162): signal clock_h is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(163): signal clk1hz is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(164): signal mclk_tmp is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(165): signal hclk_tmp is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at digital_clk.vhd(186): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(206): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(215): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(234): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(243): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(276): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(282): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(304): OTHERS choice is never selected
Warning: VHDL Process Statement warning at digital_clk.vhd(314): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(315): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(316): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(320): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(321): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(322): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(326): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(327): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(328): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(332): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(333): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(334): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(339): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(340): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(341): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(346): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(347): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(348): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(353): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(354): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(355): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(360): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(361): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(362): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(367): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(368): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(373): signal blink is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(374): signal blink is in statement, but is not in sensitivity list
Info: Inferred 8 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: hour[0]~1
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: clock_h[0]~5
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: min[0]~1
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: clock_m[0]~6
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: count[0]~4
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: i75~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: sec[0]~1
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: i109~0
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/sign_div_unsign.tdf
    Info: Found entity 1: sign_div_unsign
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/alt_u_div.tdf
    Info: Found entity 1: alt_u_div
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file ../../../../quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Info: Implemented 258 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 16 output pins
    Info: Implemented 237 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 64 warnings
    Info: Processing ended: Thu Dec 25 14:27:17 2008
    Info: Elapsed time: 00:00:04