?? start900.lst
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A51 MACRO ASSEMBLER START900 04/30/2007 17:15:54 PAGE 1
MACRO ASSEMBLER A51 V8.00
OBJECT MODULE PLACED IN START900.OBJ
ASSEMBLER INVOKED BY: E:\Program Files\keil\C51\BIN\A51.EXE START900.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;------------------------------------------------------------------------------
2 ; This file is part of the C51 Compiler package
3 ; Startup Code for the Philips LPC9xx devices
4 ; Copyright (c) 1988-2006 Keil Elektronik GmbH and Keil Software, Inc.
5 ; Version 2.4
6 ;
7 ; *** <<< Use Configuration Wizard in Context Menu >>> ***
8 ;------------------------------------------------------------------------------
9 ; START900.A51: This code is executed after processor reset.
10 ; You may add this file to a uVision2 project.
11 ;
12 ; To translate this file use Ax51 with the following invocation:
13 ;
14 ; Ax51 START900.A51 "your options"
15 ;
16 ; To link the modified START900.OBJ file to your application use the following
17 ; Lx51 invocation:
18 ;
19 ; Lx51 your object file list, START900.OBJ controls
20 ;
21 ;------------------------------------------------------------------------------
22 ;
23 ; User-defined <h> Power-On Initialization of Memory
24 ;
25 ; With the following statements the initialization of memory
26 ; at processor reset can be defined:
27 ;
28 ; <o> IDATALEN: IDATA memory length <0x0-0x100>
29 ; <i> Notes: The absolute start-address of IDATA memory is always 0
30 ; <i> The IDATA space overlaps physically the DATA and BIT areas of the
31 ; <i> LPC9xx device.
0100 32 IDATALEN EQU 0x100 ; the length of IDATA memory in bytes.
33 ;
34 ; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF>
35 ; <i>the absolute start-address of XDATA memory
0000 36 XDATASTART EQU 0
37 ;
38 ; <o> XDATALEN: XDATA memory length <0x0-0xFFFF>
39 ; <i>the length of XDATA memory in bytes.
0000 40 XDATALEN EQU 0
41 ;
42 ; </h>
43 ;------------------------------------------------------------------------------
44 ;
45 ; <h> Reentrant Stack Initialization
46 ;
47 ; The following EQU statements define the stack pointer for reentrant
48 ; functions and initialized it:
49 ;
50 ; <h> Stack Space for reentrant functions in the SMALL model.
51 ; <q> IBPSTACK: Enable SMALL model reentrant stack
52 ; <i> Stack space for reentrant functions in the SMALL model.
0000 53 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
54 ; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
55 ; <i> Set the top of the stack to the highest location.
0100 56 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
57 ; </h>
58 ;
A51 MACRO ASSEMBLER START900 04/30/2007 17:15:54 PAGE 2
59 ; <h> Stack Space for reentrant functions in the LARGE model.
60 ; <q> XBPSTACK: Enable LARGE model reentrant stack
61 ; <i> Stack space for reentrant functions in the LARGE model.
0000 62 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
63 ; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0x1FF>
64 ; <i> Set the top of the stack to the highest location.
0200 65 XBPSTACKTOP EQU 0x1FF +1 ; default 01FFH+1
66 ; </h>
67 ;
68 ; <h> Stack Space for reentrant functions in the COMPACT model.
69 ; <q> PBPSTACK: Enable COMPACT model reentrant stack
70 ; <i> Stack space for reentrant functions in the COMPACT model.
0000 71 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
72 ; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFF>
73 ; <i> Set the top of the stack to the highest location.
0100 74 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
75 ; </h>
76 ; </h>
77 ;------------------------------------------------------------------------------
78 ;
79 ; Setup LPC9xx Configuration Register (UCFG1, BOOTVEC, BOOTSTAT, SEC0..SEC7)
80 ; <h> Configuration UCFG1
81 ; Oscillator Configuration (UCFG1.0 .. UCFG1.2)
82 ; <o> FOSC: (UCFG1.0 .. UCFG1.2)
83 ; FOCS Val Description
84 ; -------- -----------
85 ; <0=> high frequency crystal or resonator (4MHz .. 20MHz)
86 ; <1=> medium frequency crystal or resonator (100kHz .. 4MHz)
87 ; <2=> low frequency crystal (20kHz .. 100kHz)
88 ; <3=> internal RC oscillator (7.373MHz +/- 2.5 percent)
89 ; <4=> internal Watchdog oscillator (400kHz +20/-30 percent)
90 ; <7=> external clock input on X1
91 ; <i> Oscillator Configuration
0003 92 FOSC EQU 3 ; default on unprogrammed parts: 3 = internal RC oscillator
93 ;
94 ; <o> IRCDBL: (UCFG1.3)
95 ; IRCDBL Val Description
96 ; ---------- -----------
97 ; <0=> 7.373 MHz standard RC oscillator clock
98 ; <1=> 14.745 MHz double RC oscillator clock
99 ; <i> clock doubling mode (0 = default on unprogrammed part)
0000 100 IRCDBL EQU 0 ; default on unprogrammed parts: 0 standard clock
101 ;
102 ; <o> WDSE: (UCFG1.4)
103 ; WDSE Val Description
104 ; -------- -----------
105 ; <0=> User can set WDT-Osc. as clock source
106 ; <1=> WDT is running with WDT-Osc.
107 ; <i> Watchdog Saftey Enable (0 = default on unprogrammed part)
0000 108 WDSE EQU 0 ; 0 = user can set WDCLK to select clock source(default on unprogrammed part)
109 ;
110 ; <o> BOE: (UCFG1.5)
111 ; BOE Val Description
112 ; ------- -----------
113 ; <0=> Disable
114 ; <1=> Enable
115 ; <i> Brownout Detect Enable (1 = default on unprogrammed part)
0001 116 BOE EQU 1
117 ;
118 ; <o> RPE: (UCFG1.6)
119 ; RPE Val Description
120 ; -------- -----------
121 ; <0=> Disable (P1.5 can use as input pin)
122 ; <1=> Enable (P1.5 used as reset pin)
123 ; <i> Reset PIN enable (0 = default on unprogrammed part)
0000 124 RPE EQU 0
A51 MACRO ASSEMBLER START900 04/30/2007 17:15:54 PAGE 3
125 ;
126 ; <o> WDTE: (UCFG1.7)
127 ; WDTE Val Description
128 ; -------- -----------
129 ; <0=> Disable (WDSE has no effect)
130 ; <1=> Enable
131 ; <i> Watchdog timer enable (0 = default on unprogrammed part)
0000 132 WDTE EQU 0
133 ; </h>
134 ;
135 ; <h> Boot Program
136 ; <o> BSB: (BOOTSTAT.0)
137 ; BSB Val Description
138 ; ------- -----------
139 ; <0=> Disable ISP entry on power-up
140 ; <1=> Enable ISP entry on power-up
141 ; <i> enables In-System Programming (ISP) power-up
0000 142 BOOTSTAT EQU 0
143 ;
144 ;
145 ; BOOTVECTOR (BOOTVEC)
146 ; --------------------
147 ; <o> ISP entry point <0x0-0x1F00:0x100> <# /0x100>
148 ; <i> points to ISP entry point (default c:0x1E00 on unprogrammed part)
001E 149 BOOTVEC EQU 0x1E ;
150 ; </h>
151 ;
152 ; <h> Flash Security Configuration
153 ; <h> SECO: (SEC0.0 .. SEC0.2)
154 ; SEC0 Val Description
155 ; -------- -----------
156 ; <q.0> Disable reading with MOVC
157 ; <q.1> Disable program/erase
158 ; <q.2> Disable IAP/ISP global erase
159 ; <i> Flash Security Configuration sector 0 (c:0x0000 - c:0x03FF)
0000 160 SEC0 EQU 0
161 ; </h>
162
163 ; <h> SEC1: (SEC1.0 .. SEC1.2)
164 ; SEC1 Bit Description
165 ; -------- -----------
166 ; <q.0> Disable reading with MOVC
167 ; <q.1> Disable program/erase
168 ; <q.2> Disable IAP/ISP global erase
169 ; <i> Flash Security Configuration sector 0 (c:0x0400 - c:0x07FF)
0000 170 SEC1 EQU 0
171 ; </h>
172
173 ; <h> SEC2: (SEC2.0 .. SEC2.2)
174 ; SEC2 Bit Description
175 ; -------- -----------
176 ; <q.0> Disable reading with MOVC
177 ; <q.1> Disable program/erase
178 ; <q.2> Disable IAP/ISP global erase
179 ; <i> Flash Security Configuration sector 0 (c:0x0800 - c:0x0BFF)
0000 180 SEC2 EQU 0
181 ; </h>
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