# BEGIN Project OptionsSET flowvendor = OtherSET vhdlsim = FalseSET verilogsim = TrueSET workingdirectory = "F:\ServU\zhaojia\RS\code version1\Fifo\ip_fifo\fifo2_clk\tmp"SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = FalseSET addpads = False# SET outputdirectory = "F:\ServU\zhaojia\RS\code version1\verilog code\Fifo\ip_fifo\fifo2_clk\"SET device = xc4vlx100# SET projectname = fifo2_clkSET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff1513SET createndf = FalseSET designentry = VerilogSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Fifo_Generator family Xilinx,_Inc. 2.0# END Select# BEGIN ParametersCSET write_data_count=falseCSET almost_empty_flag=falseCSET full_threshold_negate_value=768CSET fifo_implementation_type=Asynchronous_FifoCSET empty_threshold_negate_value=256CSET output_data_width=8CSET memory_type=Block_MemoryCSET input_depth=256CSET valid_flag=falseCSET write_acknowledge_flag=falseCSET programmable_empty_type=No_PROG_EMPTY_output_pinCSET underflow_flag=falseCSET write_data_count_width=2CSET register_outputs=falseCSET valid_sense=Active_HighCSET read_write_clock_domains=Independent_ClocksCSET data_count_width=2CSET output_depth=256CSET dout_reset_value=1CSET underflow_sense=Active_HighCSET component_name=asyncfifo256CSET overflow_sense=Active_HighCSET overflow_flag=falseCSET read_data_count=falseCSET data_count=falseCSET primitive_depth=1024CSET programmable_full_type=No_PROG_FULL_output_pinCSET read_data_count_width=2CSET read_latency=1CSET full_threshold_assert_value=768CSET almost_full_flag=falseCSET write_acknowledge_sense=Active_HighCSET empty_threshold_assert_value=256CSET input_data_width=8# END ParametersGENERATE