//****************************************************//// This controller provides timing synchronization    //// among all four modules (SC, KES, CSEE and FIFO     //// Registers). It consists of 2 FSMs that operate on  //// different clock phases.                            //// With these FSMs, it is possible for SC block to    //// get new received word data, while CSEE is still    //// correcting old data. It is no need to wait the     //// CSEE block to correct old data completely.         //// So, it can minimize throughput bottleneck          //// to only in KES block.                              ////****************************************************//module MainControl(start, reset, clock1, clock2, finish_kes,                  errdetect, rootcntr, lambda_degree, active_sc,                   active_kes, active_csee,                   evalsynd, holdsynd,                   errfound, decode_fail, ready, dataoutstart,                   dataoutend,                     en_infifo, en_outcsee,                      lastdataout, evalerror,en_sccell,en_rd_fifo);input start, reset;input clock1, clock2;input errdetect, finish_kes;input [3:0] rootcntr, lambda_degree;output active_sc, active_kes, active_csee, ready;output evalsynd, holdsynd, errfound, decode_fail;output dataoutstart, dataoutend;output  reg en_sccell;output   en_infifo, en_outcsee;output lastdataout, evalerror;output reg en_rd_fifo;reg  [3:0]lambda_degree_reg;reg active_sc, active_kes, active_csee;reg ready, decode_fail, evalsynd, holdsynd, errfound;reg   en_infifo, en_outcsee;reg encntdataout, encntdatain;reg [7:0] cntdatain, cntdataout;reg dataoutstart, dataoutend;reg datainfinish;wire lastdataout;parameter [4:0] st1_0=0, st1_1=1, st1_2=2, st1_3=3, st1_4=4, st1_5=5,                 st1_6=6, st1_7=7, st1_8=8, st1_9=9, st1_10=10,                 st1_11=11, st1_12=12, st1_13=13, st1_14=14,st1_17=15,st1_18=16;reg [4:0] state1, nxt_state1;parameter [3:0] st2_0=0, st2_1=1, st2_2=2, st2_3=3, st2_4=4, st2_5=5,                st2_6=6, st2_7=7, st2_8=8, st2_9=9, st2_10=10,                st2_11=11;reg [3:0] state2, nxt_state2;//***************************************************////                    FSM 1                          ////***************************************************//always@(posedge clock1 or negedge reset)begin    if(~reset)      state1 = st1_0;    else      state1 = nxt_state1;    endalways@(state1 or start or rootcntr or lambda_degree_reg or errdetect          or datainfinish or finish_kes or dataoutend)begin   case(state1)        st1_0 : begin                if(start)                  nxt_state1 = st1_1;                else                  nxt_state1 = st1_0;                end        st1_1 : nxt_state1 = st1_2;        st1_2 : begin                if(datainfinish)                   nxt_state1 = st1_3;                else                   nxt_state1 = st1_2;                end           st1_3 : begin                if(errdetect)                   nxt_state1 = st1_4;                else                   nxt_state1 = st1_18;                end        st1_4 : nxt_state1 = st1_5;        st1_5 : begin                if(finish_kes)                  nxt_state1 = st1_6;                else                   nxt_state1 = st1_5;                end        st1_6 : nxt_state1 = st1_17;        st1_17: nxt_state1 = st1_7;        st1_7 : begin                if((~start)&&(~dataoutend))                   nxt_state1 = st1_7;                else if(dataoutend)                   begin                       if(lambda_degree_reg == rootcntr)                          nxt_state1 = st1_0;                       else                          nxt_state1 = st1_10;                   end                else                   nxt_state1 = st1_8;                end        st1_8 : begin                if(dataoutend)                   begin                      if(lambda_degree_reg == rootcntr)                         nxt_state1 = st1_2;                      else                         nxt_state1 = st1_11;                   end                else                   nxt_state1 = st1_9;                end        st1_9 : begin                if(dataoutend)                   begin                      if(lambda_degree_reg == rootcntr)                         nxt_state1 = st1_2;                      else                         nxt_state1 = st1_11;                   end                else                   nxt_state1 = st1_9;                end         st1_10: begin                if(start)                   nxt_state1 = st1_1;                else                   nxt_state1 = st1_0;                end        st1_11: begin                if(datainfinish)                   nxt_state1 = st1_3;                else                   nxt_state1 = st1_2;                end         st1_18 :  nxt_state1 = st1_12;                      st1_12: begin                if((~start)&&(~dataoutend))                   nxt_state1 = st1_12;                else if(dataoutend)                   nxt_state1 = st1_0;                else                   nxt_state1 = st1_13;                end        st1_13: begin                if(dataoutend)                   nxt_state1 = st1_2;                else                   nxt_state1 = st1_14;                end        st1_14: begin                if(dataoutend)                   nxt_state1 = st1_2;                else                   nxt_state1 = st1_14;                end       default: nxt_state1 = st1_0;   endcaseend// Output logic of FSM1 //always@(state1)begin    case(state1)        st1_0 :begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end        st1_1 :begin               ready = 1;               active_sc = 1;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end                 st1_2 :begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end        st1_3 :begin               ready = 0;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 1;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end        st1_4 :begin               ready = 0;               active_sc = 0;               active_kes = 1;               active_csee = 0;               evalsynd = 0;               errfound = 1;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end        st1_5 :begin               ready = 0;               active_sc = 0;               active_kes =0;// 1;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo =0;               end        st1_6 :begin               ready = 0;               active_sc = 0;               active_kes = 0;//1;               active_csee = 1;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;               en_rd_fifo=0;               end        st1_17:begin               ready = 1;               active_sc = 0;               active_kes = 0;//1;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;               en_rd_fifo =0;               end                st1_7 :begin               ready = 1;               active_sc = 0;               active_kes = 0;//1;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;               en_rd_fifo =1;               end                st1_8 :begin               ready = 1;               active_sc = 1;               active_kes = 0;//1;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;               en_rd_fifo =1;               end                   st1_9 :begin               ready = 1;               active_sc = 0;               active_kes = 0;//1;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;                     en_rd_fifo =1;               end                   st1_10:begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 1;               en_outcsee = 0;                     en_rd_fifo =0;               end        st1_11:begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 1;               en_outcsee = 0;                     en_rd_fifo =0;               end        st1_18:begin               ready = 1;               active_sc = 0;               active_kes = 0;