active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;               en_rd_fifo =0;               end        st1_12:begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;                     en_rd_fifo =1;               end        st1_13:begin               ready = 1;               active_sc = 1;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;                en_rd_fifo =1;               end        st1_14:begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 1;                en_rd_fifo =1;               end       default:begin               ready = 1;               active_sc = 0;               active_kes = 0;               active_csee = 0;               evalsynd = 0;               errfound = 0;               decode_fail = 0;               en_outcsee = 0;                en_rd_fifo =0;               end    endcaseend       //****************************************// //                 FSM 2                  ////****************************************//always@(posedge clock2 or negedge reset)begin   if(~reset)      state2 = st2_0;   else      state2 = nxt_state2;end      always@(state2 or active_sc or cntdatain or lastdataout or en_outcsee)begin   case(state2)      st2_0 : begin              if(active_sc)                 nxt_state2 = st2_1;              else                 nxt_state2 = st2_0;              end      st2_1 : begin              if(cntdatain == 203)                 nxt_state2 = st2_2;              else                 nxt_state2 = st2_1;              end      st2_2 : nxt_state2 = st2_3;      st2_3 : begin              if(en_outcsee)                 nxt_state2 = st2_4;              else                 nxt_state2 = st2_3;              end      st2_4 : begin              if(active_sc)                 nxt_state2 = st2_8;              else                 nxt_state2 = st2_5;              end      st2_5 : begin              if(active_sc)                 nxt_state2 = st2_9;              else                 nxt_state2 = st2_6;              end      st2_6 : begin              if(active_sc)                 nxt_state2 = st2_9;              else if((lastdataout) && (~active_sc))                 nxt_state2 = st2_7;              else                 nxt_state2 = st2_6;              end      st2_7 : begin              if(active_sc)                 nxt_state2 = st2_1;              else                 nxt_state2 = st2_0;              end      st2_8 : nxt_state2 = st2_9;      st2_9 : begin              if((lastdataout) && (cntdatain==203))                 nxt_state2 = st2_10;              else if(lastdataout)                 nxt_state2 = st2_11;              else                 nxt_state2 = st2_9;              end      st2_10: nxt_state2 = st2_3;      st2_11: begin              if(cntdatain==203)                 nxt_state2 = st2_2;              else                 nxt_state2 = st2_1;              end      default: nxt_state2 = st2_0;   endcaseend// Output logic of FSM 2 //always@(state2)begin    case(state2)        st2_0 : begin                dataoutstart = 0;                dataoutend = 0;                                             en_infifo = 0;                encntdatain = 0;                encntdataout = 0;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end        st2_1 : begin                dataoutstart = 0;                dataoutend = 0;                               en_infifo = 1;                encntdatain = 1;                encntdataout = 0;                holdsynd = 0;                datainfinish = 0;                en_sccell=1;                end        st2_2 : begin                dataoutstart = 0;                dataoutend = 0;                              en_infifo = 1;                encntdatain = 0;                encntdataout = 0;                holdsynd = 0;                datainfinish = 1;                en_sccell=1;                end        st2_3 : begin                dataoutstart = 0;                dataoutend = 0;                               en_infifo = 0;                encntdatain = 0;                encntdataout = 0;                holdsynd = 1;                datainfinish = 0;                en_sccell=0;                end        st2_4 : begin                dataoutstart = 0;                dataoutend = 0;                               en_infifo = 0;                encntdatain = 0;                encntdataout = 1;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end        st2_5 : begin                dataoutstart = 1;                dataoutend = 0;                              en_infifo = 0;                encntdatain = 0;                encntdataout = 1;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end        st2_6 : begin                dataoutstart = 0;                dataoutend = 0;                               en_infifo = 0;                encntdatain = 0;                encntdataout = 1;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end        st2_7 : begin                dataoutstart = 0;                dataoutend = 1;                             en_infifo = 0;                encntdatain = 0;                encntdataout = 0;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end        st2_8 : begin                dataoutstart = 1;                dataoutend = 0;                               en_infifo = 1;                encntdatain = 1;                encntdataout = 1;                holdsynd = 0;                datainfinish = 0;                en_sccell=1;                end        st2_9 : begin                dataoutstart = 0;                dataoutend = 0;                                en_infifo = 1;                encntdatain = 1;                encntdataout = 1;                holdsynd = 0;                datainfinish = 0;                en_sccell=1;                end        st2_10: begin                dataoutstart = 0;                dataoutend = 1;                            en_infifo = 1;                encntdatain = 0;                encntdataout = 0;                holdsynd = 0;                datainfinish = 1;                en_sccell=1;                end        st2_11: begin                dataoutstart = 0;                dataoutend = 1;                         en_infifo = 1;                encntdatain = 1;                encntdataout = 0;                holdsynd = 0;                datainfinish = 0;                en_sccell=1;                end       default: begin                dataoutstart = 0;                dataoutend = 0;                              en_infifo = 0;                encntdatain = 0;                encntdataout = 0;                holdsynd = 0;                datainfinish = 0;                en_sccell=0;                end   endcase  end        //*********************//// Counter for dataout //               always@(posedge clock1)begin   if(encntdataout)      cntdataout =  cntdataout + 1;   else      cntdataout = 8'b0;end// Counter for datain //               always@(posedge clock1)begin   if(encntdatain)      cntdatain =  cntdatain + 1;   else      cntdatain = 8'b0;endalways@(posedge clock1)begin  if(~reset)    lambda_degree_reg <=0;  else if (finish_kes)  	lambda_degree_reg <=lambda_degree;  	else  	lambda_degree_reg <= lambda_degree_reg;end        // lastdataout is 1 if cntdataout = 5'b11111 //assign lastdataout = (cntdataout==204);assign evalerror = encntdataout;endmodule