library ieee;
use ieee.std_logic_1164.all;

entity i486_bus is
    generic ( --下面的時間特性基于I486DX 50
              constant t6_max     : time := 12 ns;
              constant t10_max    : time := 12 ns;
              constant t10_min    : time := 3  ns;
              constant t11_max    : time := 18 ns;
              constant t16_min    : time := 5  ns;
              constant t17_min    : time := 3  ns;
              constant t22_min    : time := 5  ns;
              constant t23_min    : time := 3  ns);
   port ( --內部總線接口
          abus : out bit_vector (31 downto 0);
          dbus : inout std_logic_vector (31 downto 0);-- := (others =>'Z');
          w_rb,ads_b : out bit := '1';
          rdy_b,clk : in bit;
          --外部總線接口
          address,w_data : in bit_vector(31 downto 0);
          r_data : out bit_vector(31 downto 0);
          wr,br : in bit;
          std,done : out bit); 
end i486_bus;

architecture simple_486_bus of i486_bus is 
type state_t is (ti,t1,t2);
signal state,next_state : state_t := ti;

begin

  --下面的進程用于產生控制信號和處理器在讀寫操作時的地址信號
  --進程根據操作的類型給總線設定相應狀態
  --在讀寫操作時done信號為低，當總線就緒接受下一請求時done信號為高
  comb_logic : process
   begin
      std <= '0';
      case (state) is
           when ti =>
                done <='1';
                if (br='1') then next_state <= t1;
                else next_state <= ti;
                end if;
                dbus <= transport (others =>'Z') after t10_min;
           when t1 =>
                done <='0';
                ads_b <= transport '0'  after t6_max;
                w_rb  <= transport wr after t6_max;
                abus <= transport address after t6_max;
                dbus <= transport (others =>'Z') after t10_min;
                next_state <=t2;
           when t2 =>
                ads_b <= transport '1'  after t6_max;
                --讀操作
                if (wr='0') then 
                     if (rdy_b ='0') then
                           r_data <= to_bitvector(dbus);
                           std <= '1';
                           done <='1';
                           if (br = '0') then next_state <= ti;
                           else next_state <= t1;
						   end if;
                     else next_state <= t2;
                     end if;
                 --寫操作
                 else
                     dbus <= transport to_stdlogicvector(w_data) after t10_max;
                     if (rdy_b= '0') then
                          done <='1';
                          if (br = '0') then next_state <= ti;
                          else next_state <=t1;
                          end if;
                     else next_state <=t2;
                     end if;
                end if;
      end case;
      wait on state,rdy_b,br,dbus;
end process comb_logic;

--本進程用于在每一個時鐘上升沿更新當前狀態
seq_logic : process (clk)
begin
   if (clk='1') then state <= next_state; end if;
end process seq_logic;

--本進程用于檢查所有的建立和保持時間是否與
--所有的輸入控制信號相匹配
wave_check : process (clk,dbus,rdy_b)
  variable clk_last_rise : time := 0 ns;
begin
   if (now /= 0 ns) then
        --檢查信號建立時間
        if  clk'event and clk ='1' then
            --下面的assert語句中假定RDY的建立時間
            --大于或等于data的建立時間
            assert (rdy_b /= '0') or (wr /='0') or (now - dbus'last_event >= t22_min)
                    report "i486 bus : data setup too short"
                    severity warning;
            assert (rdy_b'last_event >= t16_min)
                    report "i486 bus : rdy setup too short"
                    severity warning;
        end if;
        --檢查保持時間
        if (dbus'event) then
            --下面的assert語句中假定RDY的保持時間
            --大于或等于data的保持時間
            assert (rdy_b /= '0') or (wr /='0') or (now - clk_last_rise >= t23_min)
                    report "i486 bus : data hold too short"
                    severity warning;
        end if;
        if (rdy_b'event) then

            assert (now - clk_last_rise >= t17_min)
                    report "i486 bus : rdy signal hold too short"
                    severity warning;
        end if;
   end if;
end process wave_check;
end simple_486_bus;