?? 100vhdl+
字號(hào):
--Page :293,294
--Objective :More glitches in inertial model
--Filename : test_18e.vhd
--Author :Joseph Pick
entity Test_18e is
end Test_18e;
architecture Behave_1 of Test_18e is
signal A : BIT := '0';
signal B : BIT := '0';
signal C : BIT := '0';
begin
Gen_Wave:
process
begin
A <= '1' after 5 ns,
'0' after 12ns;
wait;
end process Gen_Wave;
Analysis_C:
process
variable Var_C : BIT := '0';
begin
wait on C'TRANSACTION;
Var_C := C;
end process Analysis_C;
Update_C:C <= A and B after 40 ns;
Finish:
process
begin
wait for 100 ns;
assert false report "End of Simulation" severity error;
end process Finish;
end Behave_1;
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