{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 23 13:18:29 2008 " "Info: Processing started: Wed Apr 23 13:18:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MYDSP2812 -c MYDSP2812 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MYDSP2812 -c MYDSP2812" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "L:/MYDSP2812/MYDSP2812.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file L:/MYDSP2812/MYDSP2812.v" { { "Info" "ISGN_ENTITY_NAME" "1 MYDSP2812 " "Info: Found entity 1: MYDSP2812" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MYDSP2812 " "Info: Elaborating entity \"MYDSP2812\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SPI_CS MYDSP2812.v(191) " "Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(191): variable \"SPI_CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 191 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SPI_CS MYDSP2812.v(193) " "Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(193): variable \"SPI_CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 193 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SPI_CS MYDSP2812.v(194) " "Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(194): variable \"SPI_CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 194 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SPI_CS MYDSP2812.v(195) " "Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(195): variable \"SPI_CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 195 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SPI_CS MYDSP2812.v(196) " "Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(196): variable \"SPI_CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 196 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "LED_CSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"LED_CSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "MY485_CSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"MY485_CSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "M_CSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"M_CSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "DAFSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"DAFSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "SDSPI_CSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"SDSPI_CSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "AICCSn MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"AICCSn\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "CPLD_NFCE MYDSP2812.v(189) " "Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable \"CPLD_NFCE\", which holds its previous value in one or more paths through the always construct" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "NMI MYDSP2812.v(66) " "Warning (10034): Output port \"NMI\" at MYDSP2812.v(66) has no driver" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 66 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "INT2 MYDSP2812.v(68) " "Warning (10034): Output port \"INT2\" at MYDSP2812.v(68) has no driver" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 68 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "CPLD_NFCE MYDSP2812.v(189) " "Info (10041): Inferred latch for \"CPLD_NFCE\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "AICCSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"AICCSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "SDSPI_CSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"SDSPI_CSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "DAFSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"DAFSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "M_CSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"M_CSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MY485_CSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"MY485_CSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "LED_CSn MYDSP2812.v(189) " "Info (10041): Inferred latch for \"LED_CSn\" at MYDSP2812.v(189)" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 189 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_ONEWAY_BIDIR_CONNECTION" "CPLDSPI_SIMO SPI_SIMO MYDSP2812.v(76) " "Warning (10665): Bidirectional port \"SPI_SIMO\" at MYDSP2812.v(76) has a one-way connection to bidirectional port \"CPLDSPI_SIMO\"" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 76 0 0 } }  } 0 10665 "Bidirectional port \"%2!s!\" at %3!s! has a one-way connection to bidirectional port \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_ONEWAY_BIDIR_CONNECTION" "GPIOB\[14\] CPLD_SDA MYDSP2812.v(82) " "Warning (10665): Bidirectional port \"CPLD_SDA\" at MYDSP2812.v(82) has a one-way connection to bidirectional port \"GPIOB\[14\]\"" {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 82 0 0 } }  } 0 10665 "Bidirectional port \"%2!s!\" at %3!s! has a one-way connection to bidirectional port \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "SPI_SOMI " "Warning: The bidir \"SPI_SOMI\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 75 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IFCLK " "Warning: The bidir \"IFCLK\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 93 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IOPORT\[1\] " "Warning: The bidir \"IOPORT\[1\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 115 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IOPORT\[2\] " "Warning: The bidir \"IOPORT\[2\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 115 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IOPORT\[3\] " "Warning: The bidir \"IOPORT\[3\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 115 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IOPORT\[4\] " "Warning: The bidir \"IOPORT\[4\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 115 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "IOPORT\[5\] " "Warning: The bidir \"IOPORT\[5\]\" has no source; inserted an always disabled tri-state buffer." {  } { { "L:/MYDSP2812/MYDSP2812.v" "" { Text "L:/MYDSP2812/MYDSP2812.v" 115 -1 0 } }  } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}