library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tlc_7258 is
port(clk:in std_logic;
     a_b,wr,cs:out std_logic);
end;

architecture aa of tlc_7258 is
begin
 process(clk) 
 begin 
 if rising_edge(clk) then
   a_b<='1';
   wr<='0';
   cs<='0';
 end if;
 end process;
end;