Simulator report for dds
Fri Jul 20 15:48:24 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------+
; Simulator Summary ;
+------+------------+
; Type ; Value      ;
+------+------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+------------------+
; Coverage Summary ;
+------+-----------+
; Type ; Value     ;
+------+-----------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage                     ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jul 20 15:48:23 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dds -c dds
Error: Can't continue timing simulation because delay annotation information for design is missing
Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings
    Error: Processing ended: Fri Jul 20 15:48:23 2007
    Error: Elapsed time: 00:00:02